The resistor divider at the VS pin
determines the output voltage regulation point of the flyback converter. Also, the
high-side divider resistor (RS1) determines the line voltage at which the
controller enables continuous DRV operation. RS1 is initially determined
based on transformer auxiliary-to-primary turns ratio and desired input voltage
operating threshold.
Equation 38.
where
- NPA is the transformer
primary-to-auxiliary turns ratio
- VIN(run) is the ACRMS voltage to enable
turn-on of the controller (run); in case of DC input, leave out the √
2 term in the equation
- VSL(run) is the run threshold for the current
pulled out of the VS pin during the switch on-time (see the Electrical
Characteristics section of the UCC28742 data sheet)
Equation 39.
Equation 40.
The low-side VS pin resistor is
selected based on the desired VOUT regulation voltage in open-loop
conditions and sets the maximum allowable voltage during open-loop conditions.
Equation 41.
where
- VOV is the maximum
allowable peak voltage at the converter output
- VF is the
output-rectifier forward drop at near-zero current
- NAS is the transformer
auxiliary-to-secondary turns ratio
- VOVPTH is the
overvoltage detection threshold at the VS input (see the Electrical
Characteristics section of the UCC28742 data sheet)
Equation 42.
Equation 43.
The UCC28742 device maintains tight CC
regulation over varying input lines by using the line-compensation feature. The
line-compensation resistor (RLC) value is determined by the current
flowing in RS1 and the total internal gate drive and external MOSFET
turn-off delay. Assuming an internal delay of 50 ns in the UCC28742 device:
Equation 44.
where
- tD is the
current-sense delay including MOSFET turn-off delay
- KLC is a current-scaling constant (see the
Electrical Characteristics section of the UCC28742 data sheet)
Equation 45.
Equation 46.