Product details

Sample rate (max) (Msps) 500 Resolution (bps) 8 Number of input channels 2 Interface type Parallel LVDS Analog input BW (MHz) 1700 Features Low Power Rating Catalog Peak-to-peak input voltage range (V) 0.87 Power consumption (typ) (mW) 1400 Architecture Folding Interpolating SNR (dB) 48 ENOB (bit) 7.5 SFDR (dB) 55 Operating temperature range (°C) -40 to 85 Input buffer No
Sample rate (max) (Msps) 500 Resolution (bps) 8 Number of input channels 2 Interface type Parallel LVDS Analog input BW (MHz) 1700 Features Low Power Rating Catalog Peak-to-peak input voltage range (V) 0.87 Power consumption (typ) (mW) 1400 Architecture Folding Interpolating SNR (dB) 48 ENOB (bit) 7.5 SFDR (dB) 55 Operating temperature range (°C) -40 to 85 Input buffer No
HLQFP (NNB) 128 484 mm² 22 x 22
  • Internal Sample-and-Hold
  • Single +1.9V ±0.1V Operation
  • Choice of SDR or DDR Output Clocking
  • Multiple ADC Synchronization Capability
  • Specified No Missing Codes
  • Serial Interface for Extended Control
  • Fine Adjustment of Input Full-Scale Range and Offset
  • Duty Cycle Corrected Sample Clock

Key Specifications

  • Resolution: 8 Bits
  • Max Conversion Rate: 500 MSPS (min)
  • Bit Error Rate: 10-18 (typ)
  • ENOB @ 250 MHz Input: 7.5 Bits (typ)
  • DNL: ±0.15 LSB (typ)
  • Power Consumption
    • Operating: 1.4 W (typ)
    • Power Down Mode: 3.5 mW (typ)

All trademarks are the property of their respective owners.

  • Internal Sample-and-Hold
  • Single +1.9V ±0.1V Operation
  • Choice of SDR or DDR Output Clocking
  • Multiple ADC Synchronization Capability
  • Specified No Missing Codes
  • Serial Interface for Extended Control
  • Fine Adjustment of Input Full-Scale Range and Offset
  • Duty Cycle Corrected Sample Clock

Key Specifications

  • Resolution: 8 Bits
  • Max Conversion Rate: 500 MSPS (min)
  • Bit Error Rate: 10-18 (typ)
  • ENOB @ 250 MHz Input: 7.5 Bits (typ)
  • DNL: ±0.15 LSB (typ)
  • Power Consumption
    • Operating: 1.4 W (typ)
    • Power Down Mode: 3.5 mW (typ)

All trademarks are the property of their respective owners.

The ADC08D502 is a dual, low power, high performance CMOS analog-to-digital converter that digitizes signals to 8 bits resolution at sampling rates up to 500 MSPS. Consuming a typical 1.4 Watts at 500 MSPS from a single 1.9 Volt supply, this device is specified to have no missing codes over the full operating temperature range. The unique folding and interpolating architecture, the fully differential comparator design, the innovative design of the internal sample-and-hold amplifier and the self-calibration scheme enable a very flat response of all dynamic parameters beyond Nyquist, producing a high 7.5 ENOB with a 250 MHz input signal and a 500 MHz sample rate while providing a 10-18 B.E.R. Output formatting is offset binary and the LVDS digital outputs are compatible with IEEE 1596.3-1996, with the exception of an adjustable common mode voltage between 0.8V and 1.2V.

Each converter has a 1:2 demultiplexer that feeds two LVDS buses and reduces the output data rate on each bus to half the sampling rate.

The converter typically consumes less than 3.5 mW in the Power Down Mode and is available in a 128-lead, thermally enhanced exposed pad HLQFP and operates over the Industrial (-40°C ≤ TA ≤ +85°C) temperature range.

The ADC08D502 is a dual, low power, high performance CMOS analog-to-digital converter that digitizes signals to 8 bits resolution at sampling rates up to 500 MSPS. Consuming a typical 1.4 Watts at 500 MSPS from a single 1.9 Volt supply, this device is specified to have no missing codes over the full operating temperature range. The unique folding and interpolating architecture, the fully differential comparator design, the innovative design of the internal sample-and-hold amplifier and the self-calibration scheme enable a very flat response of all dynamic parameters beyond Nyquist, producing a high 7.5 ENOB with a 250 MHz input signal and a 500 MHz sample rate while providing a 10-18 B.E.R. Output formatting is offset binary and the LVDS digital outputs are compatible with IEEE 1596.3-1996, with the exception of an adjustable common mode voltage between 0.8V and 1.2V.

Each converter has a 1:2 demultiplexer that feeds two LVDS buses and reduces the output data rate on each bus to half the sampling rate.

The converter typically consumes less than 3.5 mW in the Power Down Mode and is available in a 128-lead, thermally enhanced exposed pad HLQFP and operates over the Industrial (-40°C ≤ TA ≤ +85°C) temperature range.

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* Data sheet ADC08D502 Hi Perf, Low Power, Dual 8-Bit, 500 MSPS A/D Conv datasheet (Rev. A) 02 Apr 2013

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ADC08D502 IBIS Model

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