DS90LV032AQML-SP

ACTIVE

3-V LVDS quad CMOS differential line receiver

DS90LV032AQML-SP

ACTIVE

Product details

Function Receiver Protocols LVDS Number of transmitters 0 Number of receivers 4 Supply voltage (V) 3.3 Signaling rate (Mbps) 400 Input signal LVDS Output signal LVTTL Rating Space Operating temperature range (°C) -55 to 85
Function Receiver Protocols LVDS Number of transmitters 0 Number of receivers 4 Supply voltage (V) 3.3 Signaling rate (Mbps) 400 Input signal LVDS Output signal LVTTL Rating Space Operating temperature range (°C) -55 to 85
CFP (NAD) 16 62.9285 mm² 9.91 x 6.35
  • Low chip to chip skew
  • Low differential skew
  • High impedance LVDS inputs with power-off
  • Low power dissipation
  • Accepts small swing (330 mV) differential signal levels.
  • Compatible with ANSI/TIA/EIA-644
  • Operating temperature range (-55°C to +85°C)
  • Pin compatible with DS90C032A and DS26C32A.
  • Typical Rise/Fall time is 350pS.

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  • Low chip to chip skew
  • Low differential skew
  • High impedance LVDS inputs with power-off
  • Low power dissipation
  • Accepts small swing (330 mV) differential signal levels.
  • Compatible with ANSI/TIA/EIA-644
  • Operating temperature range (-55°C to +85°C)
  • Pin compatible with DS90C032A and DS26C32A.
  • Typical Rise/Fall time is 350pS.

All trademarks are the property of their respective owners.

The DS90LV032A is a quad CMOS differential line receiver designed for applications requiring ultra low power dissipation and high data rates.

The DS90LV032A accepts low voltage (350 mV typical) differential input signals and translates them to 3V CMOS output levels. The receiver supports a TRI-STATE function that may be used to multiplex outputs.

The DS90LV032A and companion LVDS line driver (eg. DS90LV031A) provide a new alternative to high power PECL/ECL devices for high speed point-to-point interface applications.

In addition, the DS90LV032A provides power-off high impedance LVDS inputs. This feature assures minimal loading effect on the LVDS bus lines when VCC is not present.

The DS90LV032A is a quad CMOS differential line receiver designed for applications requiring ultra low power dissipation and high data rates.

The DS90LV032A accepts low voltage (350 mV typical) differential input signals and translates them to 3V CMOS output levels. The receiver supports a TRI-STATE function that may be used to multiplex outputs.

The DS90LV032A and companion LVDS line driver (eg. DS90LV031A) provide a new alternative to high power PECL/ECL devices for high speed point-to-point interface applications.

In addition, the DS90LV032A provides power-off high impedance LVDS inputs. This feature assures minimal loading effect on the LVDS bus lines when VCC is not present.

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Technical documentation

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Type Title Date
* Data sheet DS90LV032AQML 3V LVDS Quad CMOS Differential Line Receiver datasheet (Rev. A) 16 Apr 2013
Application brief DLA Approved Optimizations for QML Products (Rev. A) PDF | HTML 05 Jun 2024
Selection guide TI Space Products (Rev. J) 12 Feb 2024
More literature TI Engineering Evaluation Units vs. MIL-PRF-38535 QML Class V Processing (Rev. A) 31 Aug 2023
Application note Heavy Ion Orbital Environment Single-Event Effects Estimations (Rev. A) PDF | HTML 17 Nov 2022
Application note Single-Event Effects Confidence Interval Calculations (Rev. A) PDF | HTML 19 Oct 2022
Application brief How Far, How Fast Can You Operate LVDS Drivers and Receivers? 03 Aug 2018
Application brief How to Terminate LVDS Connections with DC and AC Coupling 16 May 2018
More literature Die D/S DS90LV032 MDS 3V LVDS Quad Cmos Differential Line Receiver 07 Sep 2012

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

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Simulation model

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CFP (NAD) 16 Ultra Librarian

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