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2A Peak Sink/Source DDR Termination Regulator with VTTREF Buffered Reference for DDR2/3/3L/4


Models (3)

Title Category Type Date
TPS51206 TINA-TI Transient Reference Design TINA-TI Reference Design TSC 30 Nov 2011
TPS51206 TINA-TI Transient Spice Model TINA-TI Spice Model ZIP 30 Nov 2011
TPS51206 PSpice Transient Model PSpice Model ZIP 10 Aug 2011

Design kits & evaluation modules (1)

Name Part# Type
2-A Peak Sink/Source DDR Termination Regulator With VTTREF Buffered Reference TPS51206EVM-745 Evaluation Modules & Boards

Reference designs

High efficiency power supply architecture reference design for protection relay processor module

This reference design showcases various power architectures for generating multiple voltage rails for an application processor module, requiring >1A load current and high efficiency . The required power supply is generated using 5-, 12- or 24-V DC input from the backplane. Power supplies are (...)

View the Important Notice for reference designs covering authorized use, intellectual property matters and disclaimers.

Description Part Number Company Tool Type
Altera Stratix Vgx Reference Design PMP9284 Texas Instruments Reference designs
Power Solution for Xilinx FPGA Zynq 7 (1.8V@0.15A) PMP8251 Texas Instruments Reference designs

WEBENCH® Designer TPS51206

DDR type
Ambient Temp  °C 0 to 85°C