Dual-Channel, 16-Bit, 800-MSPS, 1x-8x Interpolating Digital-to-Analog Converter (DAC) - DAC5688


Dual-Channel, 16-Bit, 800-MSPS, 1x-8x Interpolating Digital-to-Analog Converter (DAC)



The DAC5688 is a dual-channel 16-bit 800 MSPS digital-to-analog converter (DAC) with dual CMOS digital data bus, integrated 2x-8x interpolation filters, a fine frequency mixer with 32-bit complex numerically controlled oscillator (NCO), on-board clock multiplier, IQ compensation, and internal voltage reference. Different modes of operation enable or bypass various signal processing blocks. The DAC5688 offers superior linearity, noise, crosstalk and PLL phase noise performance.

The DAC5688 dual CMOS data bus provides 250 MSPS input data transfer per DAC channel. Several input data options are available: dual-bus data, single-bus interleaved data, even and odd multiplexing at half-rate, and an input FIFO with either external or internal clock to ease interface timing. Input data can interpolated 2x, 4x or 8x by on-board digital interpolating FIR filters with over 80 dB of stop-band attenuation.

The DAC5688 allows both complex or real output. An optional 32-bit NCO/mixer in complex mode provides frequency upconversion and the dual DAC output produces a complex Hilbert Transform pair. A digital Inverse SINC filter compensates for natural DAC sin(x)/x frequency roll-off. The digital Quadrature Modulator Correction (QMC) feature allows IQ compensation of phase, gain and offset to maximize sideband rejection and minimize LO feed-through of an external quadrature modulator performing the final single sideband RF up-conversion.

The DAC5688 is pin compatible with the DAC5689 which does not include a clock-multiplying PLL. The DAC5688 is characterized for operation over the industrial temperature range of –40°C to 85°C and is available in a 64-pin 9x9mm QFN package.


  • Dual, 16-Bit, 800 MSPS DACs
  • Dual, 16-Bit, 250 MSPS CMOS Input Data
    • 16 Sample Input FIFO
    • Flexible input data bus options
  • High Performance
    • 81 dBc ACLR WCDMA TM1 at 70 MHz
  • 2x-32x Clock Multiplying PLL/VCO
  • Selectable 2x–8x Interpolation Filters
    • Stop-band Attenuation > 80 dB
  • Complex Mixer with 32-Bit NCO
  • Digital Quadrature Modulator Correction
    • Gain, Phase and Offset Correction
  • Digital Inverse SINC Filter
  • 3- or 4-Wire Serial Control Interface
  • On Chip 1.2-V Reference
  • Differential Scalable Output: 2 to 20 mA
  • Package: 64-pin 9×9mm QFN
    • Cellular Base Stations
    • Broadband Wireless Access (BWA)
    • WiMAX 802.16
    • Fixed Wireless Backhaul
    • Cable Modem Termination System (CMTS)

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Parametrics Compare all products in High Speed DAC (>10MSPS)

Internal PLL
Resolution (Bits)
Sample / Update Rate (MSPS)
DAC: Channels
Supply Voltage(s) (V)
IMD3 (dBc)
Power Consumption (Typ) (mW)
Operating Temperature Range (C)
Package Group
Package Size: mm2:W x L (PKG)
Approx. Price (US$)
Output Range Max. (mA)
Output Range Min. (mA)
Output Type
Reference: Type
DAC5688 DAC5687 DAC5689
Yes    Yes     
16    16    16   
800    500    800   
2    2    2   
Parallel CMOS    Parallel CMOS    Parallel CMOS   
80    80    80   
1.8, 3.3    1.8, 3.3    1.8, 3.3   
85    79    85   
1750    1410    1750   
-40 to 85    -40 to 85    -40 to 85   
64VQFN: 81 mm2: 9 x 9(VQFN)    100HTQFP: 256 mm2: 16 x 16(HTQFP)    64VQFN: 81 mm2: 9 x 9(VQFN)   
29.95 | 1ku    28.59 | 1ku    30.40 | 1ku   
Catalog    Catalog    Catalog   
Current Sink    Current Sink    Current Sink   
20    20    20   
2    2    2   
Differential    Differential    Differential   
Int    Int    Int