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AM5K2E04

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Sitara-Prozessor: Vierfach-Arm Cortex-A15

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AM5K2E04

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Produktdetails

Arm CPU 4 Arm Cortex-A15 Arm (max) (MHz) 1250, 1400 Coprocessors Network co-processor CPU 32-bit Protocols Ethernet Ethernet MAC 8-Port 1Gb switch PCIe 4 PCIe Gen 2 Hardware accelerators Packet Accelerator, Security Accelerator Features Networking Operating system Linux, RTOS Rating Catalog Operating temperature range (°C) -40 to 100
Arm CPU 4 Arm Cortex-A15 Arm (max) (MHz) 1250, 1400 Coprocessors Network co-processor CPU 32-bit Protocols Ethernet Ethernet MAC 8-Port 1Gb switch PCIe 4 PCIe Gen 2 Hardware accelerators Packet Accelerator, Security Accelerator Features Networking Operating system Linux, RTOS Rating Catalog Operating temperature range (°C) -40 to 100
FCBGA (ABD) 1089 729 mm² 27 x 27
  • ARM® Cortex®-A15 MPCore™ CorePac
    • Up to Four ARM Cortex-A15 Processor Cores at
      up to 1.4-GHz
    • 4MB L2 Cache Memory Shared by all Cortex-
      A15 Processor Cores
    • Full Implementation of ARMv7-A Architecture
      Instruction Set
    • 32KB L1 Instruction and Data Caches per Core
    • AMBA 4.0 AXI Coherency Extension (ACE)
      Master Port, Connected to MSMC (Multicore
      Shared Memory Controller) for Low Latency
      Access to SRAM and DDR3
  • Multicore Shared Memory Controller (MSMC)
    • 2 MB SRAM Memory for ARM CorePac
    • Memory Protection Unit for Both SRAM and
      DDR3_EMIF
  • Multicore Navigator
    • 8k Multi-Purpose Hardware Queues with Queue
      Manager
    • One Packet-Based DMA Engine for Zero-
      Overhead Transfers
  • Network Coprocessor
    • Packet Accelerator Enables Support for
      • Transport Plane IPsec, GTP-U, SCTP,
        PDCP
      • L2 User Plane PDCP (RoHC, Air Ciphering)
      • 1 Gbps Wire Speed Throughput at 1.5
        MPackets Per Second
    • Security Accelerator Engine Enables Support for
      • IPSec, SRTP, 3GPP and WiMAX Air
        Interface, and SSL/TLS Security
      • ECB, CBC, CTR, F8, A5/3, CCM, GCM,
        HMAC, CMAC, GMAC, AES, DES, 3DES,
        Kasumi, SNOW 3G, SHA-1, SHA-2 (256-bit
        Hash), MD5
      • Up to 6.4 Gbps IPSec and 3 Gbps Air
        Ciphering
    • Ethernet Subsystem
      • Eight SGMII Ports with Wire Rate Switching
      • IEEE1588 v2 (with Annex D/E/F) Support
      • 8 Gbps Total Ingress/Egress Ethernet BW
        from Core
      • Audio/Video Bridging (802.1Qav/D6.0)
      • QOS Capability
      • DSCP Priority Mapping
  • Peripherals
    • Two PCIe Gen2 Controllers with Support for
      • Two Lanes per Controller
      • Supports Up to 5 GBaud
    • One HyperLink
      • Supports Connections to Other KeyStone Architecture
        Devices Providing Resource
        Scalability
      • Supports Up to 50 GBaud
    • 10-Gigabit Ethernet (10-GbE) Switch Subsystem
      • Two SGMII/XFI Ports with Wire Rate
        Switching and MACSEC Support
      • IEEE1588 v2 (with Annex D/E/F) Support
    • One 72-Bit DDR3/DDR3L Interface with Speeds Up
      to 1600 MTPS in DDR3 Mode
    • EMIF16 Interface
    • Two USB 2.0/3.0 Controllers
    • USIM Interface
    • Two UART Interfaces
    • Three I2C Interfaces
    • 32 GPIO Pins
    • Three SPI Interfaces
    • One TSIP
      • Support 1024 DS0s
      • Support 2 Lanes at 32.768/16.3848.192
        Mbps Per Lane
  • System Resources
    • Three On-Chip PLLs
    • SmartReflex Automatic Voltage Scaling
    • Semaphore Module
    • Twelve 64-Bit Timers
    • Five Enhanced Direct Memory Access (EDMA)
      Modules
  • Commercial Case Temperature:
    • 0°C to 85°C
  • Extended Case Temperature:
    • –40°C to 100°C
  • ARM® Cortex®-A15 MPCore™ CorePac
    • Up to Four ARM Cortex-A15 Processor Cores at
      up to 1.4-GHz
    • 4MB L2 Cache Memory Shared by all Cortex-
      A15 Processor Cores
    • Full Implementation of ARMv7-A Architecture
      Instruction Set
    • 32KB L1 Instruction and Data Caches per Core
    • AMBA 4.0 AXI Coherency Extension (ACE)
      Master Port, Connected to MSMC (Multicore
      Shared Memory Controller) for Low Latency
      Access to SRAM and DDR3
  • Multicore Shared Memory Controller (MSMC)
    • 2 MB SRAM Memory for ARM CorePac
    • Memory Protection Unit for Both SRAM and
      DDR3_EMIF
  • Multicore Navigator
    • 8k Multi-Purpose Hardware Queues with Queue
      Manager
    • One Packet-Based DMA Engine for Zero-
      Overhead Transfers
  • Network Coprocessor
    • Packet Accelerator Enables Support for
      • Transport Plane IPsec, GTP-U, SCTP,
        PDCP
      • L2 User Plane PDCP (RoHC, Air Ciphering)
      • 1 Gbps Wire Speed Throughput at 1.5
        MPackets Per Second
    • Security Accelerator Engine Enables Support for
      • IPSec, SRTP, 3GPP and WiMAX Air
        Interface, and SSL/TLS Security
      • ECB, CBC, CTR, F8, A5/3, CCM, GCM,
        HMAC, CMAC, GMAC, AES, DES, 3DES,
        Kasumi, SNOW 3G, SHA-1, SHA-2 (256-bit
        Hash), MD5
      • Up to 6.4 Gbps IPSec and 3 Gbps Air
        Ciphering
    • Ethernet Subsystem
      • Eight SGMII Ports with Wire Rate Switching
      • IEEE1588 v2 (with Annex D/E/F) Support
      • 8 Gbps Total Ingress/Egress Ethernet BW
        from Core
      • Audio/Video Bridging (802.1Qav/D6.0)
      • QOS Capability
      • DSCP Priority Mapping
  • Peripherals
    • Two PCIe Gen2 Controllers with Support for
      • Two Lanes per Controller
      • Supports Up to 5 GBaud
    • One HyperLink
      • Supports Connections to Other KeyStone Architecture
        Devices Providing Resource
        Scalability
      • Supports Up to 50 GBaud
    • 10-Gigabit Ethernet (10-GbE) Switch Subsystem
      • Two SGMII/XFI Ports with Wire Rate
        Switching and MACSEC Support
      • IEEE1588 v2 (with Annex D/E/F) Support
    • One 72-Bit DDR3/DDR3L Interface with Speeds Up
      to 1600 MTPS in DDR3 Mode
    • EMIF16 Interface
    • Two USB 2.0/3.0 Controllers
    • USIM Interface
    • Two UART Interfaces
    • Three I2C Interfaces
    • 32 GPIO Pins
    • Three SPI Interfaces
    • One TSIP
      • Support 1024 DS0s
      • Support 2 Lanes at 32.768/16.3848.192
        Mbps Per Lane
  • System Resources
    • Three On-Chip PLLs
    • SmartReflex Automatic Voltage Scaling
    • Semaphore Module
    • Twelve 64-Bit Timers
    • Five Enhanced Direct Memory Access (EDMA)
      Modules
  • Commercial Case Temperature:
    • 0°C to 85°C
  • Extended Case Temperature:
    • –40°C to 100°C

The AM5K2E0x is a high performance device based on TI’s KeyStone II Multicore SoC Architecture, incorporating the most performance-optimized Cortex-A15 processor dual-core or quad-core CorePac that can run at a core speed of up to 1.4 GHz. TI’s AM5K2E0x device enables a high performance, power-efficient and easy to use platform for developers of a broad range of applications such as enterprise grade networking end equipment, data center networking, avionics and defense, medical imaging, test and automation.

TI’s KeyStone II Architecture provides a programmable platform integrating various subsystems (for example, ARM CorePac (Cortex-A15 Processor Quad Core CorePac), network processing, and uses a queue-based communication system that allows the device resources to operate efficiently and seamlessly. This unique device architecture also includes a TeraNet switch that enables the wide mix of system elements, from programmable cores to high-speed IO, to each operate at maximum efficiency with no blocking or stalling.

The AM5K2E0x KeyStone II device integrates a large amount of on-chip memory. The Cortex-A15 processor cores each have 32KB of L1Data and 32KB of L1 Instruction cache. The up to four Cortex A15 cores in the ARM CorePac share a 4MB L2 Cache. The device also integrates 2MB of Multicore Shared Memory (MSMC) that can be used as a shared L3 SRAM. All L2 and MSMC memories incorporate error detection and error correction. For fast access to external memory, this device includes a 64-bit DDR-3 (72-bit with ECC support) external memory interface (EMIF) running at 1600 MTPS.

The device enables developers to use a variety of development and debugging tools that include GNU GCC, GDB, Open source Linux, Eclipse based debugging environment enabling kernel and user space debugging using a variety of Eclipse plug-ins including TI's industry leading IDE Code Composer Studio.

The AM5K2E0x is a high performance device based on TI’s KeyStone II Multicore SoC Architecture, incorporating the most performance-optimized Cortex-A15 processor dual-core or quad-core CorePac that can run at a core speed of up to 1.4 GHz. TI’s AM5K2E0x device enables a high performance, power-efficient and easy to use platform for developers of a broad range of applications such as enterprise grade networking end equipment, data center networking, avionics and defense, medical imaging, test and automation.

TI’s KeyStone II Architecture provides a programmable platform integrating various subsystems (for example, ARM CorePac (Cortex-A15 Processor Quad Core CorePac), network processing, and uses a queue-based communication system that allows the device resources to operate efficiently and seamlessly. This unique device architecture also includes a TeraNet switch that enables the wide mix of system elements, from programmable cores to high-speed IO, to each operate at maximum efficiency with no blocking or stalling.

The AM5K2E0x KeyStone II device integrates a large amount of on-chip memory. The Cortex-A15 processor cores each have 32KB of L1Data and 32KB of L1 Instruction cache. The up to four Cortex A15 cores in the ARM CorePac share a 4MB L2 Cache. The device also integrates 2MB of Multicore Shared Memory (MSMC) that can be used as a shared L3 SRAM. All L2 and MSMC memories incorporate error detection and error correction. For fast access to external memory, this device includes a 64-bit DDR-3 (72-bit with ECC support) external memory interface (EMIF) running at 1600 MTPS.

The device enables developers to use a variety of development and debugging tools that include GNU GCC, GDB, Open source Linux, Eclipse based debugging environment enabling kernel and user space debugging using a variety of Eclipse plug-ins including TI's industry leading IDE Code Composer Studio.
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Technische Dokumentation

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Typ Titel Datum
* Data sheet AM5K2E04/02 Multicore ARM KeyStone II System-on-Chip (SoC) datasheet (Rev. D) 11 Mär 2015
* Errata AM5K2E04/02 KeyStone SoC Silicon Errata (Silicon Rev 1.0) (Rev. B) 20 Aug 2015
User guide ARM Assembly Language Tools v20.2.0.LTS User's Guide (Rev. Z) PDF | HTML 30 Mär 2023
User guide ARM Optimizing C/C++ Compiler v20.2.0.LTS User's Guide (Rev. W) PDF | HTML 30 Mär 2023
Application note DDR3 Design Requirements for KeyStone Devices (Rev. D) PDF | HTML 07 Jul 2022
Application note Using Arm ROM Bootloader on Keystone II Devices PDF | HTML 04 Jun 2019
User guide ARM Assembly Language Tools v19.6.0.STS User's Guide (Rev. X) 03 Jun 2019
User guide ARM Optimizing C/C++ Compiler v19.6.0.STS User's Guide (Rev. U) 03 Jun 2019
Application note Keystone Multicore Device Family Schematic Checklist PDF | HTML 17 Mai 2019
Application note KeyStone II DDR3 interface bring-up 07 Mär 2019
User guide ARM Assembly Language Tools v18.12.0.LTS User's Guide (Rev. W) 19 Nov 2018
User guide ARM Optimizing C/C++ Compiler v18.12.0.LTS User's Guide (Rev. T) 19 Nov 2018
User guide How-To and Troubleshooting Guide for PRU-ICSS PROFIBUS 24 Sep 2018
User guide ARM Assembly Language Tools v18.1.0.LTS User's Guide (Rev. U) 16 Jan 2018
User guide ARM Optimizing C/C++ Compiler v18.1.0.LTS User's Guide (Rev. R) 16 Jan 2018
User guide ARM Assembly Language Tools v17.9.0.STS User's Guide (Rev. T) 30 Sep 2017
User guide ARM Optimizing C/C++ Compiler v17.9.0.STS User's Guide (Rev. Q) 30 Sep 2017
User guide KeyStone II Architecture Universal Serial Bus 3.0 (USB 3.0) (Rev. A) 21 Aug 2017
Application note Thermal Design Guide for DSP and Arm Application Processors (Rev. B) 14 Aug 2017
User guide Phase-Locked Loop (PLL) for KeyStone Devices User's Guide (Rev. I) 26 Jul 2017
User guide ARM Assembly Language Tools v17.6.0.STS User's Guide (Rev. S) 21 Jun 2017
User guide ARM Optimizing C/C++ Compiler v17.6.0.STS User's Guide (Rev. P) 21 Jun 2017
Application note Power Consumption Summary for K2E System-on-Chip (SoC) Device Family 14 Jun 2017
Application note Clocking Spreadsheet for K2E Device Family 26 Jan 2017
User guide Serializer/Deserializer (SerDes) for KeyStone II Devices User Guide (Rev. A) 27 Jul 2016
Application note Power Management of KS2 Device (Rev. C) 15 Jul 2016
User guide ARM Assembly Language Tools v16.9.0.LTS User's Guide (Rev. P) 30 Apr 2016
User guide ARM Optimizing C/C++ Compiler v16.9.0.LTS User's Guide (Rev. M) 30 Apr 2016
Application note Throughput Performance Guide for KeyStone II Devices (Rev. B) 22 Dez 2015
Application note Keystone II DDR3 Debug Guide 16 Okt 2015
User guide Enhanced Direct memory Access 3 (EDMA3) for KeyStone Devices User's Guide (Rev. B) 06 Mai 2015
User guide Gigabit Ethernet (GbE) Switch SS for K2E & K2L Devices User's Guide (Rev. A) 28 Apr 2015
User guide Multicore Navigator (CPPI) for KeyStone Architecture User's Guide (Rev. H) PDF | HTML 09 Apr 2015
User guide DDR3 Memory Controller for KeyStone II Devices User's Guide (Rev. C) 27 Mär 2015
White paper Save power and costs with TI's K2E on-chip networking features 25 Mär 2015
Application note Keystone II DDR3 Initialization 26 Jan 2015
User guide ARM Assembly Language Tools v5.2 User's Guide (Rev. M) 05 Nov 2014
User guide ARM Optimizing C/C++ Compiler v5.2 User's Guide (Rev. J) 05 Nov 2014
User guide Power Sleep Controller (PSC) for KeyStone Devices User's Guide (Rev. C) 04 Sep 2014
White paper KeyStone™-II-based processors: 10G Ethernet as an optical interface 25 Aug 2014
User guide Packet Accelerator 2 (PA2) for K2E and K2L Devices User's Guide 19 Aug 2014
User guide Security Accelerator 2 (SA2) for K2E and K2L Devices User's Guide 19 Aug 2014
White paper Differentiating AM5K2E02 and AM5K2E04 SoCs from Alternate ARM® Cortex®-A15 Devic 14 Aug 2014
User guide Network Coprocessor (NETCP) for K2E and K2L Devices User's Guide 13 Aug 2014
Application note Hardware Design Guide for KeyStone II Devices 24 Mär 2014
User guide PCI Express (PCIe) for KeyStone Devices User's Guide (Rev. D) 30 Sep 2013
User guide Debug and Trace for KeyStone II Devices User's Guide 26 Jul 2013
User guide ARM Bootloader User Guide for KeyStone II Devices 21 Jul 2013
User guide Memory Protection Unit (MPU) for KeyStone Devices User's Guide (Rev. A) 28 Jun 2013
User guide HyperLink for KeyStone Devices User's Guide (Rev. C) 28 Mai 2013
User guide 10 Gigabit Ethernet Switch Subsystem User Guide for KeyStone II Devices 08 Feb 2013
User guide Multicore Shared Memory Controller (MSMC) User Guide for KeyStone II Devices 12 Nov 2012
Product overview Industrial Imaging: Applications of the K2H and K2E platforms 09 Nov 2012
Product overview Video Infrastructure - Applications of the K2E, K2H platforms 09 Nov 2012
User guide ARM CorePac User Guide for KeyStone II Devices 31 Okt 2012
Application note Multicore Programming Guide (Rev. B) 29 Aug 2012
User guide Serial Peripheral Interface (SPI) for KeyStone Devices User’s Guide (Rev. A) 30 Mär 2012
User guide Chip Interrupt Controller (CIC) for KeyStone Devices User's Guide (Rev. A) 27 Mär 2012
User guide 64-Bit Timer (Timer64) for KeyStone Devices User's Guide (Rev. A) 22 Mär 2012
Application note PCIe Use Cases for KeyStone Devices 13 Dez 2011
User guide Inter-Integrated Circuit (I2C) for KeyStone Devices User's Guide 02 Sep 2011
User guide External Memory Interface (EMIF16) for KeyStone Devices User's Guide (Rev. A) 24 Mai 2011
User guide C66x DSP Cache User's Guide 09 Nov 2010
Application note Clocking Design Guide for KeyStone Devices 09 Nov 2010
User guide General-Purpose Input/Output (GPIO) forKeyStone Devices User's Guide 09 Nov 2010
Application note Optimizing Loops on the C66x DSP 09 Nov 2010
User guide Telecom Serial Interface Port (TSIP) for KeyStone Devices User's Guide 09 Nov 2010
User guide Universal Asynchronous Receiver/Transmitter (UART) for KeyStone Devices UG 09 Nov 2010

Design und Entwicklung

Weitere Bedingungen oder erforderliche Ressourcen enthält gegebenenfalls die Detailseite, die Sie durch Klicken auf einen der unten stehenden Titel erreichen.

Debug-Tastkopf

TMDSEMU200-U — XDS200-USB-Debug-Tastkopf

Die XDS200 ist eine Debug-Sonde (Emulator) zum Debuggen von Embedded-Bausteinen von TI. Die XDS200 bietet ein ausgewogenes Preis-Leistungsverhältnis im Vergleich zum preiswerten XDS110 und dem leistungsstarken XDS560v2 und unterstützt zahlreiche Standards (IEEE1149,1, IEEE1149,7, SWD) in einem (...)

Nicht verfügbar auf TI.com
Debug-Tastkopf

TMDSEMU560V2STM-U — XDS560v2 System-Trace-USB-Debug-Tastkopf

Der XDS560v2 ist die leistungsstärkste Debug-Sonde aus der XDS560™ Familie von Debug-Sonden und unterstützt sowohl den traditionellen JTAG-Standard (IEEE1149.1) als auch cJTAG (IEEE1149.7).  Bitte beachten: Diese Lösung unterstützt kein Serial Wire Debug (SWD).

Alle XDS-Debug-Tastköpfe unterstützen (...)

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Debug-Tastkopf

TMDSEMU560V2STM-UE — XDS560v2 System-Trace-USB-und Ethernet-Debug-Tastkopf

The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors that (...)

Nicht verfügbar auf TI.com
Entwicklungskit

EVMK2EX — K2E-Entwicklungsplatine

The EVMK2EX is a full-featured development tool for 66AK2Exx and AM5K2Exx KeyStone II based SoCs. Get started developing general purpose embedded computing systems for industrial, mission critical, and networking applications today with this double-wide AMC form-factor evaluation board featuring a (...)

Benutzerhandbuch: PDF
Nicht verfügbar auf TI.com
Software-Entwicklungskit (SDK)

BIOSLINUXMCSDK-K2 — MCSDK supporting SYS/BIOS RTOS and Linux OS for KeyStone II ARM A15 + DSP C66x

NOTE: K2x, C665x and C667x devices are now actively maintained on the Processor-SDK release stream. See links above.

Our Multicore Software Development Kits (MCSDK) provide highly-optimized bundles of foundational, platform-specific drivers to enable development on selected TI ARM and DSP devices. (...)

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66AK2E05 — Hochleistungs-Multicore DSP+Arm – 4x Arm A15-Kerne, 1x C66x DSP-Kern, NetCP, 10 GbE 66AK2H06 — Hochleistungs-Multicore-DSP+Arm – 2x Arm A15-Kerne, 4x C66x-DSP-Kerne 66AK2H12 — Hochleistungs-Multicore-DSP+Arm – 4x Arm A15-Kerne, 8x C66x-DSP-Kerne 66AK2H14 — Hochleistungs-Multicore-DSP+Arm – 4x Arm A15-Kerne, 8x C66x DSP-Kerne, 10 GbE AM5K2E02 — Sitara-Prozessor: Dual-Arm Cortex-A15 AM5K2E04 — Sitara-Prozessor: Vierfach-Arm Cortex-A15
Digitale Signalprozessoren (DSPs)
66AK2L06 — System-on-Chip (SoC) mit Multicore-DSP + ARM KeyStone II
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Software-Entwicklungskit (SDK)

PROCESSOR-SDK-LINUX-K2E — Linux Processor SDK for K2E

 

Processor SDK (Software Development Kit) is a unified software platform for TI embedded processors providing easy setup and fast out-of-the-box access to benchmarks and demos.  All releases of Processor SDK are consistent across TI’s broad portfolio, allowing developers to seamlessly (...)

Unterstützte Produkte und Hardware

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66AK2E05 — Hochleistungs-Multicore DSP+Arm – 4x Arm A15-Kerne, 1x C66x DSP-Kern, NetCP, 10 GbE AM5K2E02 — Sitara-Prozessor: Dual-Arm Cortex-A15 AM5K2E04 — Sitara-Prozessor: Vierfach-Arm Cortex-A15
Download-Optionen
Software-Entwicklungskit (SDK)

PROCESSOR-SDK-LINUX-RT-K2E — Linux-RT Processor SDK for K2E

 

Processor SDK (Software Development Kit) is a unified software platform for TI embedded processors providing easy setup and fast out-of-the-box access to benchmarks and demos.  All releases of Processor SDK are consistent across TI’s broad portfolio, allowing developers to seamlessly (...)

Unterstützte Produkte und Hardware

Unterstützte Produkte und Hardware

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ARM-basierte Prozessoren
66AK2E05 — Hochleistungs-Multicore DSP+Arm – 4x Arm A15-Kerne, 1x C66x DSP-Kern, NetCP, 10 GbE AM5K2E02 — Sitara-Prozessor: Dual-Arm Cortex-A15 AM5K2E04 — Sitara-Prozessor: Vierfach-Arm Cortex-A15
Download-Optionen
Software-Entwicklungskit (SDK)

PROCESSOR-SDK-RTOS-K2E — RTOS Processor SDK for K2E

 

Processor SDK (Software Development Kit) is a unified software platform for TI embedded processors providing easy setup and fast out-of-the-box access to benchmarks and demos.  All releases of Processor SDK are consistent across TI’s broad portfolio, allowing developers to seamlessly (...)

Unterstützte Produkte und Hardware

Unterstützte Produkte und Hardware

Produkte
ARM-basierte Prozessoren
66AK2E05 — Hochleistungs-Multicore DSP+Arm – 4x Arm A15-Kerne, 1x C66x DSP-Kern, NetCP, 10 GbE AM5K2E02 — Sitara-Prozessor: Dual-Arm Cortex-A15 AM5K2E04 — Sitara-Prozessor: Vierfach-Arm Cortex-A15
Download-Optionen
IDE, Konfiguration, Compiler oder Debugger

CCSTUDIO — Code Composer Studio integrated development environment (IDE)

Code Composer Studio is an integrated development environment (IDE) for TI's microcontrollers and processors. It comprises a suite of tools used to develop and debug embedded applications.  Code Composer Studio is available for download across Windows®, Linux® and macOS® (...)

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Unterstützte Produkte und Hardware

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Simulationsmodell

AM5K2E04 AM5K2E02 ABD BSDL Model

SPRM623.ZIP (28 KB) - BSDL Model
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Simulationsmodell

AM5K2E04 AM5K2E02 ABD IBIS Model

SPRM621.ZIP (2180 KB) - IBIS Model
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Simulationsmodell

AM5K2E04 AM5K2E02 ABD Thermal Model

SPRM622.ZIP (5 KB) - Thermal Model
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Simulationsmodell

AM5K2E04 and AM5K2E02 Power Consumption Model (Rev. A)

SPRM653A.ZIP (142 KB) - Power Model
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Simulationsmodell

KeyStone II IBIS AMI Models

SPRM743.ZIP (265889 KB) - IBIS-AMI Model
lock = Nur mit Exportgenehmigung (1 Minute)
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Berechnungstool

CLOCKTREETOOL — Taktbaum-Tool für Sitara, Automobilanwendungen, Sichtanalytik und digitale Signalprozessoren

The Clock Tree Tool (CTT) for Sitara™ ARM®, Automotive, and Digital Signal Processors is an interactive clock tree configuration software that provides information about the clocks and modules in these TI devices. It allows the user to:
  • Visualize the device clock tree
  • Interact with clock tree (...)
Benutzerhandbuch: PDF
Optionen anzeigen
Designtool

PROCESSORS-3P-SEARCH — Arm-basierte MPU, ARM-basierte MCU und DSP Drittanbieter-Suchtool

TI hat sich mit Unternehmen zusammengeschlossen, um eine breite Palette von Software, Tools und SOMs anzubieten, die TI-Prozessoren verwenden, damit die Produkte schneller zur Marktreife gelangen. Laden Sie dieses Suchtool herunter, um schnell unsere Drittanbieter-Lösungen zu durchsuchen und den (...)
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Schaltplan

66AK2E05 66AK2E02 AM5K2E04 AM5K2E02 ABD OrCAD Symbols

SPRR197.ZIP (99 KB)
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Referenzdesigns

TIDEP0042 — Generierung der AVS SmartReflex-Kernspannung für K2E mit TPS544C25 und PMBus – Referenzdesign

The K2E requires the use of AVS SmartReflex control for the CVDD core voltage. This design provides method of generating the proper voltage using software and the PMBus interface of the TPS544C25. The circuit can be implemented on the XEVMK2EX.
Design guide: PDF
Schaltplan: PDF
Referenzdesigns

TIDEP0041 — Generierung der AVS SmartReflex-Kernspannung, PMBus für K2E – Referenzdesign

The K2E requires the use of AVS SmartReflex control for the CVDD core voltage. This design provides method of generating the proper voltage without the need for any software. The circuit is currently implemented on the XEVMK2EX.
Design guide: PDF
Schaltplan: PDF
Referenzdesigns

TIDEP0031 — Stromversorgungssequenzierung für K2E mit UCD9090 und PMBus

The K2E devices require power supplies to be sequenced in a proper order. This design demonstrates power sequencing for the 66AK2Ex and AM5K2Ex families of KeyStone II ARM+DSP and ARM-only multicore processors by use of the UCD9090. The UCD9090 is a 10-rail PMBus/I2C addressable power-supply (...)
Design guide: PDF
Schaltplan: PDF
Referenzdesigns

TIDEP0026 — Referenzdesign für K2E Taktgenerierung

A single clock source should not be used to drive multiple clock inputs for a high-performance processor device, such as multicore ARM Cortex-A15 based 66AK2Ex and AM5K2Ex processors, since excessive loading, reflections, and noise will negatively impact performance. These can be avoided through (...)
Design guide: PDF
Schaltplan: PDF
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Bestellen & Qualität

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