TPS7H3301-SP

활성

방사능 내성 강화 QMLV, 2.3V~3.5V 입력, 3A 싱크 및 소스 DDR 터미네이션 LDO 레귤레이터

제품 상세 정보

DDR memory type DDR2, DDR3, DDR4 Control mode S3, S4/S5 Iout VTT (max) (A) 3 Iq (typ) (mA) 18 Output VREF, VTT Vin (min) (V) 0.9 Vin (max) (V) 3.5 Features Complete Solution, Shutdown Pin for S3 Rating Space Operating temperature range (°C) -55 to 125 Regulator type Linear Regulator Vin bias (max) (V) 3.5 Vin bias (min) (V) 2.375 Vout VTT (min) (V) 0.6
DDR memory type DDR2, DDR3, DDR4 Control mode S3, S4/S5 Iout VTT (max) (A) 3 Iq (typ) (mA) 18 Output VREF, VTT Vin (min) (V) 0.9 Vin (max) (V) 3.5 Features Complete Solution, Shutdown Pin for S3 Rating Space Operating temperature range (°C) -55 to 125 Regulator type Linear Regulator Vin bias (max) (V) 3.5 Vin bias (min) (V) 2.375 Vout VTT (min) (V) 0.6
CFP (HKR) 16 105.6 mm² 11 x 9.6
  • 5962R14228(1):
    • Radiation hardness assurance (RHA) qualified to total ionizing dose (TID) 100 krad(Si)
    • Single event latch-up (SEL), single event gate rupture (SEGR), single event burnout (SEB) immune to LET = 70 MeV-cm2/mg(2)
    • Single event transient (SET), single event functional interrupt (SEFI), and single event upset (SEU) characterized to 70 MeV-cm2/mg(2)
  • Supports DDR, DDR2, DDR3, DDR3L, and DDR4 termination applications
  • Input voltage: supports a 2.5-V and 3.3-V rail(3)
  • Separate low-voltage input (VLDOIN) down to
    0.9 V for improved power efficiency(3)
  • 3-A sink and source termination regulator includes droop compensation
  • Enable input and power-good output for power supply sequencing
  • VTT termination regulator
    • Output voltage range: 0.5 to 1.75 V
    • 3-A sink and source current
  • Integrated precision voltage divider network with sense input
  • Remote sensing (VTTSNS)
  • VTTREF buffered reference
    • ±15-mV accuracy
    • ±10-mA sink and source current
  • Undervoltage lockout (UVLO) and overcurrent limit (OCL) functionality integrated
  • 5962R14228(1):
    • Radiation hardness assurance (RHA) qualified to total ionizing dose (TID) 100 krad(Si)
    • Single event latch-up (SEL), single event gate rupture (SEGR), single event burnout (SEB) immune to LET = 70 MeV-cm2/mg(2)
    • Single event transient (SET), single event functional interrupt (SEFI), and single event upset (SEU) characterized to 70 MeV-cm2/mg(2)
  • Supports DDR, DDR2, DDR3, DDR3L, and DDR4 termination applications
  • Input voltage: supports a 2.5-V and 3.3-V rail(3)
  • Separate low-voltage input (VLDOIN) down to
    0.9 V for improved power efficiency(3)
  • 3-A sink and source termination regulator includes droop compensation
  • Enable input and power-good output for power supply sequencing
  • VTT termination regulator
    • Output voltage range: 0.5 to 1.75 V
    • 3-A sink and source current
  • Integrated precision voltage divider network with sense input
  • Remote sensing (VTTSNS)
  • VTTREF buffered reference
    • ±15-mV accuracy
    • ±10-mA sink and source current
  • Undervoltage lockout (UVLO) and overcurrent limit (OCL) functionality integrated

The TPS7H3301-SP is a TID and SEE radiation-hardened double data rate (DDR) 3-A termination regulator with built-in VTTREF buffer. The regulator is specifically designed to provide a complete, compact, low-noise solution for space DDR termination applications such as single board computers, solid state recorders, and payload processing.

The TPS7H3301-SP supports DDR VTT termination applications using DDR, DDR2, DDR3, DDR4. The fast transient response of the TPS7H3301-SP VTT regulator allows for a very stable supply during read/write conditions. During transients, the fast tracking feature of the VTTREF supply minimizes any voltage offset between VTT/Vo and VTTREF. To enable simple power sequencing, both an enable input and a power-good output (PGOOD) have been integrated into the TPS7H3301-SP. The PGOOD output is open-drain so it can be tied to multiple open-drain outputs to monitor when all supplies have come into regulation. The enable signal can also be used to discharge VTT/Vo during suspend to RAM (S3) power down mode.

The TPS7H3301-SP is a TID and SEE radiation-hardened double data rate (DDR) 3-A termination regulator with built-in VTTREF buffer. The regulator is specifically designed to provide a complete, compact, low-noise solution for space DDR termination applications such as single board computers, solid state recorders, and payload processing.

The TPS7H3301-SP supports DDR VTT termination applications using DDR, DDR2, DDR3, DDR4. The fast transient response of the TPS7H3301-SP VTT regulator allows for a very stable supply during read/write conditions. During transients, the fast tracking feature of the VTTREF supply minimizes any voltage offset between VTT/Vo and VTTREF. To enable simple power sequencing, both an enable input and a power-good output (PGOOD) have been integrated into the TPS7H3301-SP. The PGOOD output is open-drain so it can be tied to multiple open-drain outputs to monitor when all supplies have come into regulation. The enable signal can also be used to discharge VTT/Vo during suspend to RAM (S3) power down mode.

다운로드 스크립트와 함께 비디오 보기 동영상

기술 문서

star =TI에서 선정한 이 제품의 인기 문서
검색된 결과가 없습니다. 검색어를 지우고 다시 시도하십시오.
모두 보기21
유형 직함 날짜
* Data sheet TPS7H3301-SP Sink and Source Radiation-Hardened 3-A DDR Termination Regulator With Built-In VTTREF Buffer datasheet (Rev. B) PDF | HTML 2020/06/30
* Radiation & reliability report TPS7H3301-SP and TPS7H3302-SP Single-Event Effects Radiation Report (Rev. C) 2024/01/26
* Radiation & reliability report TPS7H3301-SP Neutron Displacement Damage Characterization 2019/04/12
* SMD TPS7H3301-SP SMD 5962-14228 2016/07/08
* Radiation & reliability report TPS7H3301-SP Total Ionizing Dose Radiation Report 2016/07/01
Application note Using Space Grade Power Components to Power AMD Kintex XQRKU060 FPGA PDF | HTML 2023/11/08
Application note Using Space Grade Power Components to Power Microchip RT PolarFire FPGA PDF | HTML 2023/09/20
More literature TI Engineering Evaluation Units vs. MIL-PRF-38535 QML Class V Processing (Rev. A) 2023/08/31
Application note QML flow, its importance, and obtaining lot information (Rev. C) 2023/08/30
Application note Space Grade Power Solution for Microsemi RTG4 PDF | HTML 2023/05/02
Application note TI Space Rated Power Solution for Microsemi® RTG4™ FPGA (Rev. B) PDF | HTML 2023/01/19
Application note Heavy Ion Orbital Environment Single-Event Effects Estimations (Rev. A) PDF | HTML 2022/11/17
Application note Single-Event Effects Confidence Interval Calculations (Rev. A) PDF | HTML 2022/10/19
Selection guide TI Space Products (Rev. I) 2022/03/03
EVM User's guide TPS7H3301EVM-CVAL User's Guide (Rev. B) 2020/10/30
Application note DLA Standard Microcircuit Drawings (SMD) and JAN Part Numbers Primer 2020/08/21
Application note DDR VTT Power Solutions: A Competitive Analysis (Rev. A) 2020/07/09
Application note Hermetic Package Reflow Profiles, Termination Finishes, and Lead Trim and Form PDF | HTML 2020/05/18
E-book Radiation Handbook for Electronics (Rev. A) 2019/05/21
Application note External Soft-Start Circuit for TPS7H3301-SP Power-Up Sequencing Applications 2016/07/07
Technical article 7 things to know about spacecraft subsystems before your next trip to Mars PDF | HTML 2016/07/06

설계 및 개발

추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.

평가 보드

TPS7H3301EVM-CVAL — TPS7H3301-SP DDR 터미네이션 LDO 레귤레이터용 평가 모듈

TPS7H3301-SP source/sink Double Data Rate (DDR) termination regulator designed to support system needs for low noise applications.

Integrated solution with reduced system solution size, improved efficiency, and simple system design integration.

사용 설명서: PDF
TI.com에서 구매할 수 없습니다
개발 키트

ALPHA-XILINX-KU060-SPACE — TI 전원을 사용하는 Xilinx® Kintex® UltraScale™ XQRKU060 FPGA용 Alpha Data® 보드

This is a development kit for the Xilinx® XQRKU060 FPGA with industrial -1 speed grade. ADA-SDEV-KIT2 has a modular board design with a XRTC-compatible configuration module, two FMC connectors, DDR3 DRAM, system monitoring, and space-grade TI power management and temperature-sensing solutions.
시뮬레이션 모델

TPS7H3301-SP PSpice Transient Model (Rev. B)

SLVMBF1B.ZIP (116 KB) - PSpice Model
시뮬레이션 모델

TPS7H3301-SP Unencrypted PSPICE Transient Model

SLVMDD2.ZIP (196 KB) - PSpice Model
계산 툴

SLVC650 TPS7H3301-SP Calculator

지원되는 제품 및 하드웨어

지원되는 제품 및 하드웨어

제품
DDR 메모리 전원 IC
TPS7H3301-SP 방사능 내성 강화 QMLV, 2.3V~3.5V 입력, 3A 싱크 및 소스 DDR 터미네이션 LDO 레귤레이터
패키지 다운로드
CFP (HKR) 16 옵션 보기

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

권장 제품에는 본 TI 제품과 관련된 매개 변수, 평가 모듈 또는 레퍼런스 디자인이 있을 수 있습니다.

지원 및 교육

TI 엔지니어의 기술 지원을 받을 수 있는 TI E2E™ 포럼

콘텐츠는 TI 및 커뮤니티 기고자에 의해 "있는 그대로" 제공되며 TI의 사양으로 간주되지 않습니다. 사용 약관을 참조하십시오.

품질, 패키징, TI에서 주문하는 데 대한 질문이 있다면 TI 지원을 방문하세요. ​​​​​​​​​​​​​​

동영상