CDCDB400
- 4 LP-HCSL outputs with programmable integrated 85-Ω (default) or 100-Ω differential output terminations
- 4 hardware output enable (OE#) controls
- Additive phase jitter after PCIE Gen 6 filter: 20 fs, RMS (maximum)
- Additive phase jitter after PCIE Gen 5 filter: 25 fs, RMS (maximum)
- Additive phase jitter after DB2000Q filter: 38 fs, RMS (maximum)
- Supports Common Clock (CC) and Individual Reference (IR) architectures
- Spread spectrum-compatible
- Output-to-output skew: < 50 ps
- Input-to-output delay: < 3 ns
-
Fail-safe input
-
Programmable output slew rate control
-
3 selectable SMBus addresses
- 3.3-V core and IO supply voltages
- Hardware-controlled low power mode (PD#)
- Current consumption: 46 mA maximum
- 5-mm × 5-mm, 32-pin VQFN package
The CDCDB400 is a 4-output LP-HCSL, DB800ZL-compliant, clock buffer capable of distributing the reference clock for PCIe Gen 1-6, QuickPath Interconnect (QPI), UPI, SAS, and SATA interfaces in CC, SRNS, or SRIS architectures. The SMBus interface and four output enable pins allow the configuration and control of all four outputs individually. The CDCDB400 is a DB800ZL derivative buffer and meets or exceeds the system parameters in the DB800ZL specification. The device also meets or exceeds the parameters in the DB2000Q specification. The CDCDB400 is packaged in a 5-mm × 5-mm, 32-pin VQFN package.
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技術文件
類型 | 標題 | 日期 | ||
---|---|---|---|---|
* | Data sheet | CDCDB400 DB800ZL-Compliant 4-Output Clock Buffer for PCIe Gen 1 to Gen 6 datasheet (Rev. A) | PDF | HTML | 2022年 5月 23日 |
設計與開發
如需其他條款或必要資源,請按一下下方的任何標題以檢視詳細頁面 (如有)。
CDCDB800EVM — CDCDB800 評估模組是適用於 PCIe® Gen 1 至 Gen 5 應用的 8 輸出 LP-HCSL 時脈緩衝器
PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
封裝 | 引腳 | 下載 |
---|---|---|
VQFN (RHB) | 32 | 檢視選項 |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 資格摘要
- 進行中可靠性監測
- 晶圓廠位置
- 組裝地點
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。