CDCLVD110A
- Low-Output Skew <30 ps (Typical) for Clock-Distribution Applications
- Distributes One Differential Clock Input to 10 LVDS Differential Clock Outputs
- VCC Range: 2.5 V ±5%
- Typical Signaling Rate Capability of Up to 1.1 GHz
- Configurable Register (SI/CK) Individually Enables Disables Outputs, Selectable CLK0, CLK0 or CLK1, CLK1 Inputs
- Full Rail-to-Rail Common-Mode Input Range
- Receiver Input Threshold: ±100 mV
- Available in 32-Pin LQFP and VQFN Package
- Fail-Safe I/O-Pins for VDD = 0 V (Power Down)
The CDCLVD110A clock driver distributes one pair of differential LVDS clock inputs (either CLK0 or CLK1) to 10 pairs of differential clock outputs (Q0 to Q9) with minimum skew for clock distribution. The CDCLVD110A is specifically designed to drive 50-Ω transmission lines.
When the control enable is high (EN = 1), the 10 differential outputs are programmable in
that each output can be individually enabled or disabled
(3-stated) according to the first 10 bits loaded into the shift register. Once the shift
register is loaded, the last bit selects either CLK0 or CLK1 as the clock input. However, when EN =
0, the outputs are not programmable and all outputs are enabled.
The CDCLVD110A has an improved start-up circuit that minimizes enabling time in AC- and DC-coupled systems.
The CDCLVD110A is characterized for operation from –40°C to 85°C.
技術文件
類型 | 標題 | 日期 | ||
---|---|---|---|---|
* | Data sheet | CDCLVD110A Programmable Low-Voltage 1:10 LVDS Clock Driver datasheet (Rev. D) | PDF | HTML | 2016年 12月 12日 |
設計與開發
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CLOCK-TREE-ARCHITECT — 時鐘樹架構程式設計軟體
PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
封裝 | 引腳 | 下載 |
---|---|---|
LQFP (VF) | 32 | 檢視選項 |
VQFN (RHB) | 32 | 檢視選項 |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 資格摘要
- 進行中可靠性監測
- 晶圓廠位置
- 組裝地點
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