CDCDB803
- 8 LP-HCSL outputs with programmable integrated 85-Ω (default) or 100-Ω differential output terminations
- 8 hardware output enable (OE#) controls
- Additive phase jitter after PCIE Gen 6 filter: 20 fs, RMS (maximum)
- Additive phase jitter after PCIE Gen 5 filter: 25 fs, RMS (maximum)
- Additive phase jitter after DB2000Q filter: 38 fs, RMS (maximum)
- Supports Common Clock (CC) and Individual Reference (IR) architectures
- Spread spectrum-compatible
- Output-to-output skew: < 50 ps
- Input-to-output delay: < 3 ns
-
Fail-safe input
-
Programmable output slew rate control
- 9 selectable SMBus addresses
- 3.3-V core and IO supply voltages
- Hardware-controlled low power mode (PD#)
- Current consumption: 72 mA maximum
- 6-mm × 6-mm, 48-pin VQFN package
The CDCDB803 is a 8-output LP-HCSL, DB800ZL-compliant, clock buffer capable of distributing the reference clock for PCIe Gen 1-6, QuickPath Interconnect (QPI), UPI, SAS, and SATA interfaces. The SMBus interface and eight output enable pins allow the configuration and control of all eight outputs individually. The CDCDB803 is a DB800ZL derivative buffer and meets or exceeds the system parameters in the DB800ZL specification. It also meets or exceeds the parameters in the DB2000Q specification. The CDCDB803 is packaged in a 6-mm × 6-mm, 48-pin VQFN package.
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檢視所有 1 類型 | 標題 | 日期 | ||
---|---|---|---|---|
* | Data sheet | CDCDB803 DB800ZL-Compliant 8-Output Clock Buffer for PCIe Gen 1 to Gen 6 datasheet (Rev. A) | PDF | HTML | 2022年 5月 23日 |
設計與開發
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開發板
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CDCDB800 評估模組是一款 8 輸出 LP-HCSL、DB800ZL 相容的時脈緩衝器,可為 PCIe® Gen 1 至 Gen 5 應用、QuickPath Interconnect (QPI)、UPI、SAS 和 SATA 介面配參考時脈。SMBus 介面及八個輸出啟用引腳可對八個輸出個別進行配置與控制。CDCDB800 是 DB800ZL衍生緩衝器,符合或超過 DB800ZL 和 DB2000Q 規格中的系統參數。
設計工具
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模擬工具
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封裝 | 引腳 | 下載 |
---|---|---|
VQFN (RSL) | 48 | 檢視選項 |
訂購與品質
內含資訊:
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 資格摘要
- 進行中可靠性監測
內含資訊:
- 晶圓廠位置
- 組裝地點
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。