計算工具
BLDC-MAX-QG-MOSFET-CALCULATOR — Calculate the maximum QG MOSFET for your motor driver
Calculate the maximum QG MOSFET that can be driven based on the PWM switching frequency, algorithm type, and additional external capacitance.
DRV8350
- 9 to 100-V, Triple half-bridge gate driver
- Optional integrated buck regulator
- Optional triple low-side current shunt amplifiers
- Smart gate drive architecture
- Adjustable slew rate control for EMI performance
- VGS handshake and minimum dead-time insertion to prevent shoot-through
- 50-mA to 1-A peak source current
- 100-mA to 2-A peak sink current
- dV/dt mitigation through strong pulldown
- Integrated gate driver power supplies
- High-side doubler charge pump For 100% PWM duty cycle control
- Low-side linear regulator
- Integrated LM5008A buck regulator
- 6 to 95-V operating voltage range
- 2.5 to 75-V, 350-mA output capability
- Integrated triple current shunt amplifiers
- Adjustable gain (5, 10, 20, 40 V/V)
- Bidirectional or unidirectional support
- 6x, 3x, 1x, and independent PWM modes
- Supports 120° sensored operation
- SPI or hardware interface available
- Low-power sleep mode (20 µA at VVM = 48-V)
- Integrated protection features
- VM undervoltage lockout (UVLO)
- Gate drive supply undervoltage (GDUV)
- MOSFET VDS overcurrent protection (OCP)
- MOSFET shoot-through prevention
- Gate driver fault (GDF)
- Thermal warning and shutdown (OTW/OTSD)
- Fault condition indicator (nFAULT)
The DRV835x family of devices are highly-integrated gate drivers for three-phase brushless DC (BLDC) motor applications. These applications include field-oriented control (FOC), sinusoidal current control, and trapezoidal current control of BLDC motors. The device variants provide optional integrated current shunt amplifiers to support different motor control schemes and a buck regulator to power the gate driver or external controller.
The DRV835x uses smart gate drive (SGD) architecture to decrease the number of external components that are typically necessary for MOSFET slew rate control and protection circuits. The SGD architecture also optimizes dead time to prevent shoot-through conditions, provides flexibility in decreasing electromagnetic interference (EMI) by MOSFET slew rate control, and protects against gate short circuit conditions through VGS monitors. A strong gate pulldown circuit helps prevent unwanted dV/dt parasitic gate turn on events
Various PWM control modes (6x, 3x, 1x, and independent) are supported for simple interfacing to the external controller. These modes can decrease the number of outputs required of the controller for the motor driver PWM control signals. This family of devices also includes 1x PWM mode for simple sensored trapezoidal control of a BLDC motor by using an internal block commutation table.
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開發板
DRV8350H-EVM — DRV8350H 三相智慧型閘極驅動器評估模組
The DRV8350H-EVM is a 15A, 3-phase brushless DC drive stage based on the DRV8350H gate driver and CSD19532Q5B NexFET™ power blocks.
The module has individual DC bus and phase voltage sense as well as an external, individual low-side current shunt amplifier, making this evaluation module ideal for (...)
使用指南: PDF
開發板
DRV8350S-EVM — DRV8350S 三相智慧型閘極驅動器評估模組
The DRV8350S-EVM is a 15A, 3-phase brushless DC drive stage based on the DRV8350S gate driver and CSD19532Q5B NexFET™ power blocks.
The module has individual DC bus and phase voltage sense as well as an external, individual low-side current shunt amplifier, making this evaluation module ideal for (...)
使用指南: PDF
| 封裝 | 引腳 | 下載 |
|---|---|---|
| WQFN (RTV) | 32 | 檢視選項 |
訂購與品質
內含資訊：
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 資格摘要
- 進行中可靠性監測
內含資訊：
- 晶圓廠位置
- 組裝地點