DS90LV028AQ-Q1
- AECQ-100 Qualified for Automotive Applications
- Temperature Grade 1: -40°C to +125°C TA
- >400 Mbps (200 MHz) Switching Rates
- 50 ps Differential Skew (Typical)
- 0.1 ns Channel-to-Channel Skew (Typical)
- 2.5 ns Maximum Propagation Delay
- 3.3V Power Supply Design
- Flow-Through Pinout
- Power Down High Impedance on LVDS Inputs
- Low Power design (18 mW at 3.3 V static)
- LVDS Inputs Accept LVDS/CML/LVPECL Signals
- Conforms to ANSI/TIA/EIA-644 Standard
- Available in SOIC Package
The DS90LV028AQ is a dual CMOS differential line receiver designed for applications requiring ultra low power dissipation, low noise and high data rates. The device is designed to support data rates in excess of 400 Mbps (200 MHz) utilizing Low Voltage Differential Signaling (LVDS) technology.
The DS90LV028AQ accepts low voltage (350 mV typical) differential input signals and translates them to 3 V CMOS output levels. The DS90LV028AQ has a flow-through design for easy PCB layout.
The DS90LV028AQ and companion LVDS line driver DS90LV027AQ provide a new alternative to high power PECL/ECL devices for high speed point-to-point interface applications.
您可能會感興趣的類似產品
引腳對引腳的功能與所比較的產品相同
技術文件
找不到結果。請清除您的搜尋條件，然後再試一次。
檢視所有 5 | 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | DS90LV028AQ-Q1 Automotive LVDS Dual Differential Line Receiver datasheet (Rev. I) | PDF | HTML | 2020年 6月 22日 |
| Application brief | LVDS to Improve EMC in Motor Drives | 2018年 9月 27日 | ||
| Application brief | How Far, How Fast Can You Operate LVDS Drivers and Receivers? | 2018年 8月 3日 | ||
| Application brief | How to Terminate LVDS Connections with DC and AC Coupling | 2018年 5月 16日 | ||
| Application note | An Overview of LVDS Technology | 1998年 10月 5日 |
設計與開發
如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。
開發板
DS90LV027A-28AEVM — 二通道 LVDS 驅動器和接收器評估模組
The DS90LV027A-28A is an evaluation module designed for performance and functional evaluation of the Texas Instruments DS90LV027A LVDS dual differential driver and DS90LV028A LVDS dual differential line receiver. With this kit, users can quickly evaluate the output waveform characteristics (...)
模擬工具
PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
模擬工具
TINA-TI — 基於 SPICE 的類比模擬程式
TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
使用指南: PDF
參考設計
TIDA-01021 — 適用於 DSO、雷達和 5G 無線測試儀的多通道 JESD204B 15 GHz 時鐘參考設計
High speed multi-channel applications require precise clocking solutions capable of managing channel-to-channel skew in order to achieve optimal system SNR, SFDR, and ENOB. This reference design is capable of supporting two high speed channels on separate boards by utilizing TI’s LMX2594 (...)
參考設計
TIDA-01022 — 適用於 DSO、雷達和 5G 無線測試系統的靈活 3.2-GSPS 多通道 AFE 參考設計
This high speed multi-channel data capture reference design enables optimum system performance. System designers needs to consider critical design parameters like clock jitter and skew for high speed multi-channel clock generation, which affects overall system SNR, SFDR, channel to channel skew (...)
參考設計
TIDA-01023 — 適用於雷達和 5G 無線測試器的高通道計數 JESD204B 時鐘產生參考設計
High-speed multi-channel applications require low noise and scalable clocking solutions capable of precise channel-to-channel skew adjustment to achieve optimal system SNR, SFDR, and ENOB. This reference design supports high channel count JESD204B synchronized clocks using one master and multiple (...)
參考設計
TIDA-01024 — 適用於雷達和 5G 無線測試器的高通道計數 JESD204B 菊輪鍊時鐘參考設計
High-speed multi-channel applications require low noise and scalable clocking solutions capable of precise channel-to-channel skew adjustment to achieve optimal system SNR, SFDR, and ENOB. This reference design supports scaling up JESD204B synchronized clocks in daisy chain configuration. This (...)
參考設計
TIDA-01027 — 在 12.8 GSPS 資料採集系統中發揮最大效能的低雜訊電源供應參考設計
This reference design demonstrates an efficient, low-noise five-rail power supply design for very high-speed Data Acquisition (DAQ) systems capable of > 12.8 GSPS. The power supply DC/DC converters are frequency-synchronized and phase-shifted in order to minimize input current ripple and (...)
參考設計
TIDA-01028 — 適用於高速示波器和寬頻帶數位器的 12.8-GSPS 類比前端參考設計
This reference design provides a practical example of interleaved RF-sampling analog-to-digital converters (ADCs) to achieve a 12.8-GSPS sampling rate. This is done by time interleaving two RF-sampling ADCs. Interleaving requires a phase shift between the ADCs, which this reference design achieves (...)
參考設計
TIDA-010128 — 適用於 12 位元數位器的可擴充 20.8 GSPS 參考設計
This reference design describes a 20.8 GSPS sampling system using RF sampling analog-to-digital converters (ADCs) in time interleaved configuration. Time interleaving method is a proven and traditional way of increasing sample rate, however, matching individual ADCs offset, gain and sampling time (...)
參考設計
TIDA-010122 — 適用於多通道射頻系統的參考設計同步數據轉換器 DDC 和 NCO 功能
此參考設計可解決與新興 5G 適配應用相關，例如大規模多輸入多輸出 (mMIMO)、相位陣列雷達與通訊酬載等應用相關的同步設計挑戰。一般 RF 前端包含天線、低雜訊放大器 (LNA)、混波器、類比網域中的本地振盪器 (LO) 及類比轉數位轉換器、數值控制振盪器 (NCO) 和數位降轉換器 (DDC)。為了達到整體系統同步化，這些數位區塊必須與系統時鐘同步。本參考設計採用 ADC12DJ3200 資料轉換器，透過同步處理晶片內建 NCO 與 SYNC ~ 並使用無雜訊孔徑延遲調整 (tAD 調整) 功能，在多個接收器之間達到小於 5-ps 的頻道間偏斜的效果，以進一步降低偏斜。此設計也具備搭載 (...)
參考設計
TIDA-010132 — 適合於雷達和電子戰應用的多通道射頻收發器參考設計
This reference design, an 8-channel analog front end (AFE), is demonstrated using two AFE7444 4-channel RF transceivers and a LMK04828-LMX2594 based clocking subsystem which can enable designs to scale to 16 or more channels. Each AFE channel consists of a 14-bit, 9-GSPS DAC and a 3-GSPS ADC that (...)
參考設計
TIDA-010131 — 適用於雷達和無線 5G 測試儀的多通道射頻收發器計時參考設計
Analog front end for high-speed end equipments like phased-array radars, wireless communication testers, and electronic warfare require synchronized, multipletransceiver signal chains. Each transceiver signal chain includes high-speed, analog-to-digital converters (ADCs), digital-to-analog (...)
| 封裝 | 引腳 | 下載 |
|---|---|---|
| SOIC (D) | 8 | 檢視選項 |
訂購與品質
內含資訊：
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 資格摘要
- 進行中可靠性監測
內含資訊：
- 晶圓廠位置
- 組裝地點
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。