LP2992

現行

具啟用功能的 250-mA、16-V、低壓差電壓穩壓器

現在提供此產品的更新版本

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TPS7A25 現行 具有電源良好功能的 300mA、18V、超低 IQ、高準確度、可調整低壓差電壓穩壓器 This is a 300-mA LDO with power good and lower IQ (2.5 μA)

產品詳細資料

Output options Fixed Output Iout (max) (A) 0.25 Vin (max) (V) 16 Vin (min) (V) 2.2 Vout (max) (V) 5 Vout (min) (V) 1.5 Fixed output options (V) 1.5, 1.8, 2.5, 3.3, 5 Noise (µVrms) 30 Iq (typ) (mA) 0.065 Thermal resistance θJA (°C/W) 72 Rating Catalog Load capacitance (min) (µF) 4.7 Regulated outputs (#) 1 Features Enable, Soft start Accuracy (%) 2 PSRR at 100 KHz (dB) 40 Dropout voltage (Vdo) (typ) (mV) 450 Operating temperature range (°C) -40 to 125
Output options Fixed Output Iout (max) (A) 0.25 Vin (max) (V) 16 Vin (min) (V) 2.2 Vout (max) (V) 5 Vout (min) (V) 1.5 Fixed output options (V) 1.5, 1.8, 2.5, 3.3, 5 Noise (µVrms) 30 Iq (typ) (mA) 0.065 Thermal resistance θJA (°C/W) 72 Rating Catalog Load capacitance (min) (µF) 4.7 Regulated outputs (#) 1 Features Enable, Soft start Accuracy (%) 2 PSRR at 100 KHz (dB) 40 Dropout voltage (Vdo) (typ) (mV) 450 Operating temperature range (°C) -40 to 125
SOT-23 (DBV) 5 8.12 mm² 2.9 x 2.8 WSON (NGD) 6 9.6068 mm² 2.92 x 3.29
  • V IN range (new chip): 2.5 V to 16 V
  • V OUT range (new chip):
    • 1.2 V to 5.0 V (fixed, 100-mV steps)
  • V OUT accuracy:
    • ±1% for A-grade legacy chip
    • ±1.5% for standard-grade legacy chip
    • ±0.5% for new chip only
  • ±1% output accuracy over load, and temperature for new chip
  • Output current: Up to 250 mA
  • Low I Q (new chip): 69 µA at I LOAD = 0 mA
  • Low I Q (new chip): 875 µA at I LOAD = 250 mA
  • Shutdown current:
    • 0.01 µA (typ) for legacy chip
    • 1.12 µA (typ) for new chip
  • Low noise: 30 µV RMS with 10-nF bypass capacitor
  • Output current limiting and thermal protection
  • Stable with 2.2-µF ceramic capacitors
  • High PSRR: 70 dB at 1 kHz, 40 dB at 1 MHz
  • Operating junction temperature: –40°C to 125°C
  • Package: 5-pin SOT-23 (DBV)
  • V IN range (new chip): 2.5 V to 16 V
  • V OUT range (new chip):
    • 1.2 V to 5.0 V (fixed, 100-mV steps)
  • V OUT accuracy:
    • ±1% for A-grade legacy chip
    • ±1.5% for standard-grade legacy chip
    • ±0.5% for new chip only
  • ±1% output accuracy over load, and temperature for new chip
  • Output current: Up to 250 mA
  • Low I Q (new chip): 69 µA at I LOAD = 0 mA
  • Low I Q (new chip): 875 µA at I LOAD = 250 mA
  • Shutdown current:
    • 0.01 µA (typ) for legacy chip
    • 1.12 µA (typ) for new chip
  • Low noise: 30 µV RMS with 10-nF bypass capacitor
  • Output current limiting and thermal protection
  • Stable with 2.2-µF ceramic capacitors
  • High PSRR: 70 dB at 1 kHz, 40 dB at 1 MHz
  • Operating junction temperature: –40°C to 125°C
  • Package: 5-pin SOT-23 (DBV)

The LP2992 is a fixed-output, wide-input, low-noise, low-dropout voltage regulator supporting an input voltage range from 2.5 V to 16 V and up to 250 mA of load current. The LP2992 supports an output range of 1.2 V to 5.0 V (for new chip).

Additionally, the LP2992 (new chip) has a 1% output accuracy across load, and temperature that can meet the needs of low-voltage microcontrollers (MCUs) and processors.

Low output noise of 30 µV RMS (with 10-nF bypass capacitors) and wide bandwidth PSRR performance of greater than 70 dB at 1 kHz and 40 dB at 1 MHz help attenuate the switching frequency of an upstream DC/DC converter and minimize post regulator filtering.

The internal soft-start time and current limit protection reduce inrush current during start up, thus minimizing input capacitance. Standard protection features, such as overcurrent and overtemperature protection, are included.

The LP2992 is available in a 5-pin 2.9-mm × 2.8-mm SOT-23 (DBV) package.

The LP2992 is a fixed-output, wide-input, low-noise, low-dropout voltage regulator supporting an input voltage range from 2.5 V to 16 V and up to 250 mA of load current. The LP2992 supports an output range of 1.2 V to 5.0 V (for new chip).

Additionally, the LP2992 (new chip) has a 1% output accuracy across load, and temperature that can meet the needs of low-voltage microcontrollers (MCUs) and processors.

Low output noise of 30 µV RMS (with 10-nF bypass capacitors) and wide bandwidth PSRR performance of greater than 70 dB at 1 kHz and 40 dB at 1 MHz help attenuate the switching frequency of an upstream DC/DC converter and minimize post regulator filtering.

The internal soft-start time and current limit protection reduce inrush current during start up, thus minimizing input capacitance. Standard protection features, such as overcurrent and overtemperature protection, are included.

The LP2992 is available in a 5-pin 2.9-mm × 2.8-mm SOT-23 (DBV) package.

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類型 標題 日期
* Data sheet LP2992 Micropower 250-mA Low-Noise Ultra-Low-Dropout Regulator in SOT-23 and WSON Packages Designed for Use With Very Low-ESR Output Capacitors datasheet (Rev. K) PDF | HTML 2023年 12月 5日
White paper Parallel LDO Architecture Design Using Ballast Resistors PDF | HTML 2022年 12月 14日
White paper Comprehensive Analysis and Universal Equations for Parallel LDO's Using Ballast PDF | HTML 2022年 12月 13日
Selection guide Low Dropout Regulators Quick Reference Guide (Rev. P) 2018年 3月 21日
Application note AN-1028 Maximum Power Enhancement Techniques for Power Packages (Rev. B) 2013年 5月 6日

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使用指南: PDF
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模擬型號

LP2992_1P5 PSpice Transient Model

SNVM642.ZIP (42 KB) - PSpice Model
模擬型號

LP2992_1P5 Unencrypted PSpice Transient Model

SNVMA91.ZIP (1 KB) - PSpice Model
模擬型號

LP2992_1P8 PSpice Transient Model

SNVM639.ZIP (39 KB) - PSpice Model
模擬型號

LP2992_1P8 TINA-TI Reference Design

SNVMA20.TSC (143 KB) - TINA-TI Reference Design
模擬型號

LP2992_1P8 TINA-TI Transient Spice Model

SNVMA19.ZIP (8 KB) - TINA-TI Spice Model
模擬型號

LP2992_1P8 Unencrypted PSpice Transient Model

SNVMA94.ZIP (1 KB) - PSpice Model
模擬型號

LP2992_2P5 PSpice Transient Model

SNVM641.ZIP (40 KB) - PSpice Model
模擬型號

LP2992_2P5 TINA-TI Reference Design

SNVMA21.TSC (168 KB) - TINA-TI Reference Design
模擬型號

LP2992_2P5 TINA-TI Transient Spice Model

SNVMA22.ZIP (8 KB) - TINA-TI Spice Model
模擬型號

LP2992_2P5 Unencrypted PSpice Transient Model

SNVMA92.ZIP (1 KB) - PSpice Model
模擬型號

LP2992_3P3 PSpice Transient Model

SNVM640.ZIP (39 KB) - PSpice Model
模擬型號

LP2992_3P3 Unencrypted PSpice Transient Model

SNVMA93.ZIP (1 KB) - PSpice Model
模擬型號

LP2992_5P0 PSpice Transient Model

SNVM643.ZIP (40 KB) - PSpice Model
模擬型號

LP2992_5P0 Unencrypted PSpice Transient Model

SNVMA90.ZIP (1 KB) - PSpice Model
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電路圖: PDF
封裝 引腳 下載
SOT-23 (DBV) 5 檢視選項
WSON (NGD) 6 檢視選項

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