SBASAI6
September 2023
ADC32RF52
PRODUCTION DATA
1
1
Features
2
Applications
3
Description
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics - Power Consumption
6.6
Electrical Characteristics - DC Specifications
6.7
Electrical Characteristics - AC Specifications (Dither DISABLED)
6.8
Electrical Characteristics - AC Specifications (Dither ENABLED)
6.9
Timing Requirements
6.10
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Analog Inputs
7.3.1.1
Input Bandwidth and Full-Scale
7.3.1.2
Input Imbalance
7.3.1.3
Overrange Indication
7.3.1.4
Analog out-of-band dither
7.3.2
Sampling Clock Input
7.3.3
SYSREF
7.3.3.1
SYSREF Capture Detection
7.3.4
ADC Foreground Calibration
7.3.4.1
Calibration Control
7.3.4.2
ADC Switch
7.3.4.3
Calibration Configuration
7.3.5
Decimation Filter
7.3.5.1
Decimation Filter Response
7.3.5.2
Decimation Filter Configuration
7.3.5.3
20-bit Output Mode
7.3.5.4
Dynamic Switching
7.3.5.4.1
2 Lane Mode
7.3.5.4.2
1 Lane Mode
7.3.5.5
Numerically Controlled Oscillator (NCO)
7.3.5.6
NCO Frequency Programming
7.3.5.7
Fast Frequency Hopping
7.3.5.7.1
Fast frequency hopping using the GPIO1/2 pins
7.3.5.7.2
Fast frequency hopping using GPIO1/2, SEN and SDATA pins
7.3.5.7.3
Fast frequency hopping using the fast SPI
7.3.6
JESD204B Interface
7.3.6.1
JESD204B Initial Lane Alignment (ILA)
7.3.6.1.1
SYNC Signal
7.3.6.2
JESD204B Frame Assembly
7.3.6.3
JESD204B Frame Assembly in Bypass Mode
7.3.6.4
JESD204B Frame Assembly with Complex Decimation - Single Band
7.3.6.5
JESD204B Frame Assembly with Complex Decimation - Dual Band
7.3.6.6
JESD204B Frame Assembly with Complex Decimation - Quad Band
7.3.7
SERDES Output MUX
7.3.8
Test Pattern
7.3.8.1
Transport Layer
7.3.8.2
Link Layer
7.3.8.3
Internal Capture Memory Buffer
7.4
Device Functional Modes
7.4.1
Digital Averaging
7.5
Programming
7.5.1
GPIO Pin Control
7.5.2
Configuration using the SPI interface
7.5.2.1
Register Write
7.5.2.2
Register Read
7.6
Register Maps
7.6.1
Detailed Register Description
8
Application and Implementation
8.1
Application Information
8.2
Typical Applications
8.2.1
Wideband RF Sampling Receiver
8.2.1.1
Design Requirements
8.2.1.1.1
Input Signal Path
8.2.1.1.2
Clocking
8.2.1.2
Detailed Design Procedure
8.2.1.2.1
Sampling Clock
8.2.1.3
Application Curves
8.3
Initialization Set Up
8.3.1
Initial Device Configuration After Power-Up
8.3.1.1
STEP 1: RESET
8.3.1.2
STEP 2: Device Configuration
8.3.1.3
STEP 3: JESD Interface Configuration (1)
8.3.1.4
STEP 4: SYSREF Synchronization
8.3.1.5
STEP 5: JESD Interface Configuration (2)
8.3.1.6
STEP 6: Analog Trim Settings
8.3.1.7
STEP 7: Calibration Configuration
8.3.1.8
STEP 8: SYSREF Synchronization
8.3.1.9
STEP 9: Run Power up Calibration
8.3.1.10
STEP 10: JESD Interface Synchronization
8.4
Power Supply Recommendations
8.5
Layout
8.5.1
Layout Guidelines
8.5.2
Layout Example
9
Device and Documentation Support
9.1
Receiving Notification of Documentation Updates
9.2
Support Resources
9.3
Trademarks
9.4
Electrostatic Discharge Caution
9.5
Glossary
10
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
RTD|64
MPQF141C
Thermal pad, mechanical data (Package|Pins)
RTD|64
QFND625
Orderable Information
sbasai6_oa
1
Features
14-Bit, dual channel 1.5-GSPS ADC
Noise spectral density:
NSD = -153 dBFS/Hz (no AVG)
NSD = -156 dBFS/Hz (2x AVG)
NSD = -159 dBFS/Hz (4x AVG)
Single core (non-interleaved) ADC architecture
Aperture jitter: 50 fs
Low close-in residual phase noise:
-133 dBc/Hz at 10 kHz offset
Spectral performance (f
IN
= 900 MHz, -4 dBFS):
2x internal averaging
SNR: 66.8 dBFS
SFDR HD2,3: 74 dBc
SFDR worst spur: 90 dBFS
Input fullscale: 1.0/1.1 Vpp (1/1.8 dBm)
Code error rate (CER): 10
-15
Full power input bandwidth (-3 dB): 1.6 GHz
JESD204B serial data interface
Maximum lane rate: 13 Gbps
Supports subclass 1 deterministic latency
Digital down-converters
Up to four DDC per ADC channel
Complex output: 4x, 16x to 128x decimation
48-bit NCO phase coherent frequency hopping
Fast frequency hopping: < 1 us
Power consumption: 1.8 W/channel (2x AVG)
Power supplies: 1.8 V, 1.2 V