SBASAI6 September   2023 ADC32RF52

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - Power Consumption
    6. 6.6  Electrical Characteristics - DC Specifications
    7. 6.7  Electrical Characteristics - AC Specifications (Dither DISABLED)
    8. 6.8  Electrical Characteristics - AC Specifications (Dither ENABLED)
    9. 6.9  Timing Requirements
    10. 6.10 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs
        1. 7.3.1.1 Input Bandwidth and Full-Scale
        2. 7.3.1.2 Input Imbalance
        3. 7.3.1.3 Overrange Indication
        4. 7.3.1.4 Analog out-of-band dither
      2. 7.3.2 Sampling Clock Input
      3. 7.3.3 SYSREF
        1. 7.3.3.1 SYSREF Capture Detection
      4. 7.3.4 ADC Foreground Calibration
        1. 7.3.4.1 Calibration Control
        2. 7.3.4.2 ADC Switch
        3. 7.3.4.3 Calibration Configuration
      5. 7.3.5 Decimation Filter
        1. 7.3.5.1 Decimation Filter Response
        2. 7.3.5.2 Decimation Filter Configuration
        3. 7.3.5.3 20-bit Output Mode
        4. 7.3.5.4 Dynamic Switching
          1. 7.3.5.4.1 2 Lane Mode
          2. 7.3.5.4.2 1 Lane Mode
        5. 7.3.5.5 Numerically Controlled Oscillator (NCO)
        6. 7.3.5.6 NCO Frequency Programming
        7. 7.3.5.7 Fast Frequency Hopping
          1. 7.3.5.7.1 Fast frequency hopping using the GPIO1/2 pins
          2. 7.3.5.7.2 Fast frequency hopping using GPIO1/2, SEN and SDATA pins
          3. 7.3.5.7.3 Fast frequency hopping using the fast SPI
      6. 7.3.6 JESD204B Interface
        1. 7.3.6.1 JESD204B Initial Lane Alignment (ILA)
          1. 7.3.6.1.1 SYNC Signal
        2. 7.3.6.2 JESD204B Frame Assembly
        3. 7.3.6.3 JESD204B Frame Assembly in Bypass Mode
        4. 7.3.6.4 JESD204B Frame Assembly with Complex Decimation - Single Band
        5. 7.3.6.5 JESD204B Frame Assembly with Complex Decimation - Dual Band
        6. 7.3.6.6 JESD204B Frame Assembly with Complex Decimation - Quad Band
      7. 7.3.7 SERDES Output MUX
      8. 7.3.8 Test Pattern
        1. 7.3.8.1 Transport Layer
        2. 7.3.8.2 Link Layer
        3. 7.3.8.3 Internal Capture Memory Buffer
    4. 7.4 Device Functional Modes
      1. 7.4.1 Digital Averaging
    5. 7.5 Programming
      1. 7.5.1 GPIO Pin Control
      2. 7.5.2 Configuration using the SPI interface
        1. 7.5.2.1 Register Write
        2. 7.5.2.2 Register Read
    6. 7.6 Register Maps
      1. 7.6.1 Detailed Register Description
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Wideband RF Sampling Receiver
        1. 8.2.1.1 Design Requirements
          1. 8.2.1.1.1 Input Signal Path
          2. 8.2.1.1.2 Clocking
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Sampling Clock
        3. 8.2.1.3 Application Curves
    3. 8.3 Initialization Set Up
      1. 8.3.1 Initial Device Configuration After Power-Up
        1. 8.3.1.1  STEP 1: RESET
        2. 8.3.1.2  STEP 2: Device Configuration
        3. 8.3.1.3  STEP 3: JESD Interface Configuration (1)
        4. 8.3.1.4  STEP 4: SYSREF Synchronization
        5. 8.3.1.5  STEP 5: JESD Interface Configuration (2)
        6. 8.3.1.6  STEP 6: Analog Trim Settings
        7. 8.3.1.7  STEP 7: Calibration Configuration
        8. 8.3.1.8  STEP 8: SYSREF Synchronization
        9. 8.3.1.9  STEP 9: Run Power up Calibration
        10. 8.3.1.10 STEP 10: JESD Interface Synchronization
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.8 Electrical Characteristics - AC Specifications (Dither ENABLED)

Maximum and minimum values are specified over the operating free-air temperature range and nominal supply voltages. Typical values are specified at TA = 25°C, ADC sampling rate = 1.5 GSPS, Bypass mode, 50% clock duty cycle, AVDD18 = 1.8 V, AVDD12, AVDDCLK, DVDD = 1.2 V, –4-dBFS differential input and dither ENABLED, unless otherwise noted
PARAMETER TEST CONDITIONS MIN(2) TYP MAX UNIT
NSD(1) Noise Spectral Density fIN = 900 MHz, AIN = -20 dBFS
no averaging		 –153.4 dBFS/Hz
fIN = 900 MHz, AIN = -20 dBFS
2x averaging		 –156.1
fIN = 900 MHz, AIN = -20 dBFS
4x averaging		 -158.7
NF(1) Noise Figure fIN = 900 MHz, AIN = -20 dBFS
no averaging		 22.2 dB
fIN = 900 MHz, AIN = -20 dBFS
2x averaging		 20.9
fIN = 900 MHz, AIN = -20 dBFS
4x averaging		 20.5
SNR(1) Signal-to-noise ratio
no averaging		 fIN = 100 MHz 63.6 dBFS
fIN = 600 MHz 64.5
fIN = 900 MHz 62.0 64.4
fIN = 900 MHz, Ain = -20 dBFS 62.3 65.2
fIN = 1.4 GHz 63.8
Signal-to-noise ratio
2x averaging		 fIN = 100 MHz 66.3
fIN = 600 MHz 66.9
fIN = 900 MHz 66.8
fIN = 900 MHz, Ain = -20 dBFS 68.0
fIN = 1.4 GHz 66.1
Signal-to-noise ratio
4x averaging		 fIN = 100 MHz 69.2
fIN = 600 MHz 69.1
fIN = 900 MHz 67.0 68.8
fIN = 900 MHz, Ain = -20 dBFS 67.7 69.5
fIN = 1.4 GHz 67.0
SINAD(1) Signal to noise and distortion ratio fIN = 100 MHz 62.2 dBFS
fIN = 600 MHz 63.4
fIN = 900 MHz 63.6
fIN = 900 MHz, Ain = -20 dBFS 64.3
fIN = 1.4 GHz 62.8
ENOB(1) Effective number of bits fIN = 100 MHz 10.3 Bits
fIN = 600 MHz 10.4
fIN = 900 MHz 10.4
fIN = 900 MHz, Ain = -20 dBFS 10.5
fIN = 1.4 GHz 10.3
THD Total Harmonic Distortion (First five harmonics) fIN = 100 MHz 68 dBc
fIN = 600 MHz 72
fIN = 900 MHz, Ain = -20 dBFS 72
fIN = 900 MHz 72
fIN = 1.4 GHz 71
HD2 Second Harmonic Distortion fIN = 100 MHz 75 dBFS
fIN = 600 MHz 75
fIN = 900 MHz 70 74
fIN = 900 MHz, Ain = -20 dBFS 84
fIN = 1.4 GHz 72
HD3 Third Harmonic Distortion fIN = 100 MHz 70 dBFS
fIN = 600 MHz 77
fIN = 900 MHz 71 79
fIN = 900 MHz, Ain = -20 dBFS 75
fIN = 1.4 GHz 81
Non HD2,3 Spur free dynamic range (excluding HD2 and HD3) fIN = 100 MHz 92 dBFS
fIN = 600 MHz 89
fIN = 900 MHz 85 90
fIN = 900 MHz, Ain = -20 dBFS 98
fIN = 1.4 GHz 94
IMD3 Two tone inter-modulation distortion f1 = 900 MHz, f2 = 1000 MHz, AIN = -10 dBFS/tone 74 84 dBFS
(1) Measured from 60 MHz to Nyquist (FS/2) excluding dither
(2) SNR, HD3 minimum values are specified by ATE, HD2 and Non HD23 are specified by bench characterization.