SBASAL3B September   2024  – June 2025 ADC3668 , ADC3669

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - Power Consumption
    6. 6.6  Electrical Characteristics - DC Specifications
    7. 6.7  Electrical Characteristics - AC Specifications (ADC3668 - 250 MSPS)
    8. 6.8  Electrical Characteristics - AC Specifications (ADC3669 - 500 MSPS)
    9. 6.9  Timing Requirements
    10. 6.10 Typical Characteristics, ADC3668
    11. 6.11 Typical Characteristics, ADC3669
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Inputs
        1. 8.3.1.1 Nyquist Zone Selection
        2. 8.3.1.2 Analog Front End Design
      2. 8.3.2 Sampling Clock Input
      3. 8.3.3 Multi-Chip Synchronization
        1. 8.3.3.1 SYSREF Monitor
      4. 8.3.4 Time-Stamp
      5. 8.3.5 Overrange
      6. 8.3.6 External Voltage Reference
      7. 8.3.7 Digital Gain
      8. 8.3.8 Decimation Filter
        1. 8.3.8.1 Uncommon Decimation Ratios
        2. 8.3.8.2 Decimation Filter Response
        3. 8.3.8.3 Decimation Filter Configuration
        4. 8.3.8.4 Numerically Controlled Oscillator (NCO)
      9. 8.3.9 Digital Interface
        1. 8.3.9.1 Parallel LVDS (DDR)
        2. 8.3.9.2 Serial LVDS (SLVDS) with Decimation
          1. 8.3.9.2.1 SLVDS - Status Bit Insertion
        3. 8.3.9.3 Output Data Format
        4. 8.3.9.4 32-bit Output Resolution
        5. 8.3.9.5 Output Scrambler
        6. 8.3.9.6 Output MUX
        7. 8.3.9.7 Test Pattern
    4. 8.4 Device Functional Modes
      1. 8.4.1 Low Latency Mode
      2. 8.4.2 Digital Channel Averaging
      3. 8.4.3 Power Down Mode
    5. 8.5 Programming
      1. 8.5.1 GPIO Programming
      2. 8.5.2 Register Write
      3. 8.5.3 Register Read
      4. 8.5.4 Device Programming
      5. 8.5.5 Register Map
      6. 8.5.6 Detailed Register Description
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Wideband Spectrum Analyzer
      2. 9.2.2 Design Requirements
        1. 9.2.2.1 Input Signal Path
        2. 9.2.2.2 Clocking
      3. 9.2.3 Detailed Design Procedure
        1. 9.2.3.1 Sampling Clock
      4. 9.2.4 Application Performance Plots
      5. 9.2.5 Initialization Set Up
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Third-Party Products Disclaimer
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.6 Electrical Characteristics - DC Specifications

Maximum and minimum values are specified over the operating free-air temperature range and nominal supply voltages. Typical values are specified at TA = 25°C, ADC sampling rate = 500 MSPS, DDC Bypass mode, 50% clock duty cycle, nominal supply voltages and –1-dBFS differential input, internal reference, unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DC ACCURACY
No missing codes 16 bits
ADC3668: 250 MSPS (INTERNAL REFERENCE)
DNL Differential nonlinearity FIN = 70 MHz -0.9 ± 0.5 LSB
INL Integral nonlinearity FIN = 70 MHz ± 2 LSB
VOS_ERR Offset error 10 LSB
VOS_DRIFT Offset drift over temperature 10 LSB
GAINERR Gain error External Reference ± 1 %FSR
Internal Reference ± 3
GAINDRIFT Gain drift over temperature External Reference ± 0.5 %FSR
Internal Reference ± 1
ADC3669: 500 MSPS (INTERNAL REFERENCE)
DNL Differential nonlinearity FIN = 70 MHz -0.9 ± 0.5 LSB
INL Integral nonlinearity FIN = 70 MHz ± 2 LSB
VOS_ERR Offset error 10 LSB
VOS_DRIFT Offset drift over temperature 10 LSB
GAINERR Gain error External Reference ± 1 %FSR
Internal Reference ± 3
GAINDRIFT Gain drift over temperature External Reference ± 0.5 %FSR
Internal Reference ± 1
ADC ANALOG INPUTS (AINP/M, BINP/M)
FS Input full scale Differential 2.0 Vpp
VICM Input common model voltage 1.3 1.4 1.5 V
ZIN Differential input impedance Differential at 100 MHz 100 Ω
VCM Output common mode voltage 1.4 V
BW Analog Input Bandwidth (-3dB) 1.4 GHz
CLOCK INPUT (CLKP/M)
Input clock frequency ADC3669 100 500 MHz
ADC3668 100 250 MHz
VID Differential input voltage 0.5 2 2.4 Vpp
VICM Input common mode voltage 0.75 V
ZIN Differential input impedance Differential at 500 MHz 5 kΩ
Clock duty cycle 35 50 65 %
EXTERNAL REFERENCE INPUT (GPIO1)
VREF External voltage reference 1.175 1.2 1.225 V
IVREF Input current, external voltage reference input 10 uA
DIGITAL INPUTS (GPIO0, GPIO1, RESET, SCLK, SEN, SDIO)
VIH High level input voltage 1.4 1.8 V
VIL Low level input voltage 0 0.4 V
IIH High level input current 90 150 uA
IIL Low level input current -150 -90 uA
CI Input capacitance 1.5 pF
DIGITAL OUTPUTS (GPIO0, GPIO1, SDIO)
VOH High level output voltage ILOAD = -400 uA AVDD18 – 0.1 AVDD18 V
VOL Low level output voltage ILOAD = 400 uA 0.1 V
LVDS/SLVDS INTERFACE (DOUT[0..15]P/M, DCLKP/M)
Output data format (default) 2s complement
VOD Differential output voltage differential peak-peak 500 700 850 mVpp
VOCM Output common mode voltage 0.96 1.02 1.08 V