SBASAP6 February   2025 ADC3683-EP , ADC3683-SEP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics - Power Consumption
    6. 5.6 Electrical Characteristics - DC Specifications
    7. 5.7 Electrical Characteristics - AC Specifications
    8. 5.8 Timing Requirements
    9. 5.9 Typical Characteristics - ADC3683
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Input
        1. 7.3.1.1 Analog Input Bandwidth
        2. 7.3.1.2 Analog Front End Design
          1. 7.3.1.2.1 Sampling Glitch Filter Design
          2. 7.3.1.2.2 Analog Input Termination and DC Bias
            1. 7.3.1.2.2.1 AC-Coupling
            2. 7.3.1.2.2.2 DC-Coupling
        3. 7.3.1.3 Auto-Zero Feature
      2. 7.3.2 Clock Input
        1. 7.3.2.1 Single Ended vs Differential Clock Input
        2. 7.3.2.2 Signal Acquisition Time Adjust
      3. 7.3.3 Voltage Reference
        1. 7.3.3.1 Internal voltage reference
        2. 7.3.3.2 External voltage reference (VREF)
        3. 7.3.3.3 External voltage reference with internal buffer (REFBUF/CTRL)
      4. 7.3.4 Digital Down Converter
        1. 7.3.4.1 DDC MUX
        2. 7.3.4.2 Digital Filter Operation
        3. 7.3.4.3 FS/4 Mixing with Real Output
        4. 7.3.4.4 Numerically Controlled Oscillator (NCO) and Digital Mixer
        5. 7.3.4.5 Decimation Filter
        6. 7.3.4.6 SYNC
        7. 7.3.4.7 Output Formatting with Decimation
      5. 7.3.5 Digital Data Path and Interface
        1. 7.3.5.1 Data Path Overview
        2. 7.3.5.2 Output Scrambler
        3. 7.3.5.3 Output Bit Mapper
          1. 7.3.5.3.1 2-Wire Mode
          2. 7.3.5.3.2 1-Wire Mode
          3. 7.3.5.3.3 ½-Wire Mode
        4. 7.3.5.4 Device Configuration Steps
          1. 7.3.5.4.1 Configuration Example
        5. 7.3.5.5 Output Data Format
      6. 7.3.6 Test Pattern
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Power Down Options
      3. 7.4.3 Digital Channel Averaging
    5. 7.5 Programming
      1. 7.5.1 Configuration using PINs only
      2. 7.5.2 Configuration using the SPI interface
        1. 7.5.2.1 Register Write
        2. 7.5.2.2 Register Read
  9. 8 Application Information Disclaimer
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Signal Path
        2. 8.2.2.2 Sampling Clock
        3. 8.2.2.3 Voltage Reference
      3. 8.2.3 Application Curves
    3. 8.3 Initialization Set Up
      1. 8.3.1 Register Initialization During Operation
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Register Map
    1. 9.1 Detailed Register Description
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Mechanical Data

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RSB|40
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.4.2 Power Down Options

A global power down mode is enabled via SPI as well as using the power down pin (PDN/SYNC). There is an internal pull-down 21kΩ resistor on the PDN/SYNC input pin and the pin is active high, so the pin must be pulled high externally to enter global power down mode.

The SPI register map provides the capability to enable/disable individual blocks directly or via PDN pin mask to trade off power consumption vs wake up time as shown in Table 7-9.

ADC3683-SEP ADC3683-EP Power Down ConfigurationsFigure 7-47 Power Down Configurations
Table 7-9 Overview of Power Down Options
Function/ RegisterPDN
via SPI		Mask for
Global PDN		Feature - DefaultPower
Impact		Wake-up
time		Comment
ADCYes-EnabledBoth ADC channels are included in Global PDN automatically
Reference gain amplifierYesYesEnabled~ 0.4mA~3usShould only be powered down in power down state.
Internal 1.2V referenceYesExternal ref~ 1-3.5mA~3msInternal/external reference selection is available through SPI and REFBUF/CTRL pin.
Clock bufferYesDifferential clock~ 1mAn/aSingle ended clock input saves ~ 1mA compared to differential.
Some programmability is available through the REFBUF/CTRL pin.
Output interface driversYes-Enabledvariesn/aDepending on output interface mode, unused output drivers is powered down for maximum power savings
Decimation filterYes-Disabledsee Electrical tablen/a