SBAS559B May   2022  – November 2025 ADS1285

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements: 1.65V ≤ IOVDD ≤ 1.95V and 2.7V ≤ IOVDD ≤ 3.6V
    7. 5.7 Switching Characteristics: 1.65V ≤ IOVDD ≤ 1.95V and 2.7V ≤ IOVDD ≤ 3.6V
    8. 5.8 Timing Diagrams
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Noise Performance
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Input
      2. 7.3.2 PGA and Buffer
        1. 7.3.2.1 Programmable Gain Amplifier (PGA)
        2. 7.3.2.2 Buffer Operation (PGA Bypass)
      3. 7.3.3 Voltage Reference Input
      4. 7.3.4 IOVDD Power Supply
      5. 7.3.5 Modulator
        1. 7.3.5.1 Modulator Overdrive
      6. 7.3.6 Digital Filter
        1. 7.3.6.1 Sinc Filter Section
        2. 7.3.6.2 FIR Filter Section
        3. 7.3.6.3 Group Delay and Step Response
          1. 7.3.6.3.1 Linear Phase Response
          2. 7.3.6.3.2 Minimum Phase Response
        4. 7.3.6.4 HPF Stage
      7. 7.3.7 Clock Input
      8. 7.3.8 GPIO
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power Modes
      2. 7.4.2 Power-Down Mode
      3. 7.4.3 Reset
      4. 7.4.4 Synchronization
        1. 7.4.4.1 Pulse-Sync Mode
        2. 7.4.4.2 Continuous-Sync Mode
      5. 7.4.5 Sample Rate Converter
      6. 7.4.6 Offset and Gain Calibration
        1. 7.4.6.1 OFFSET Register
        2. 7.4.6.2 GAIN Register
        3. 7.4.6.3 Calibration Procedure
    5. 7.5 Programming
      1. 7.5.1 Serial Interface
        1. 7.5.1.1 Chip Select (CS)
        2. 7.5.1.2 Serial Clock (SCLK)
        3. 7.5.1.3 Data Input (DIN)
        4. 7.5.1.4 Data Output (DOUT)
        5. 7.5.1.5 Data Ready (DRDY)
      2. 7.5.2 Conversion Data Format
      3. 7.5.3 Commands
        1. 7.5.3.1  Single Byte Command
        2. 7.5.3.2  WAKEUP: Wake Command
        3. 7.5.3.3  STANDBY: Software Power-Down Command
        4. 7.5.3.4  SYNC: Synchronize Command
        5. 7.5.3.5  RESET: Reset Command
        6. 7.5.3.6  Read Data Direct
        7. 7.5.3.7  RDATA: Read Conversion Data Command
        8. 7.5.3.8  RREG: Read Register Command
        9. 7.5.3.9  WREG: Write Register Command
        10. 7.5.3.10 OFSCAL: Offset Calibration Command
        11. 7.5.3.11 GANCAL: Gain Calibration Command
    6. 7.6 Register Map
      1. 7.6.1 Register Descriptions
        1. 7.6.1.1 ID/SYNC: Device ID, SYNC Register (Address = 00h) [Reset = xxxx0000b]
        2. 7.6.1.2 CONFIG0: Configuration Register 0 (Address = 01h) [Reset = 12h]
        3. 7.6.1.3 CONFIG1: Configuration Register 1 (Address = 02h) [Reset = 00h]
        4. 7.6.1.4 HPF0, HPF1: High-Pass Filter Registers (Address = 03h, 04h) [Reset = 32h, 03h]
        5. 7.6.1.5 OFFSET0, OFFSET1, OFFSET2: Offset Calibration Registers (Address = 05h, 06h, 07h) [Reset = 00h, 00h, 00h]
        6. 7.6.1.6 GAIN0, GAIN1, GAIN2: Gain Calibration Registers (Address = 08h, 09h, 0Ah) [Reset = 00h, 00h, 40h]
        7. 7.6.1.7 GPIO: Digital Input/Output Register (Address = 0Bh) [Reset = 000xx000b]
        8. 7.6.1.8 SRC0, SRC1: Sample Rate Converter Registers (Address = 0Ch, 0Dh) [Reset = 00h, 80h]
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Analog Power Supplies
      2. 8.3.2 Digital Power Supply
      3. 8.3.3 Grounds
      4. 8.3.4 Thermal Pad
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.2.1 Programmable Gain Amplifier (PGA)

The PGA is a low-noise, chopper-stabilized differential amplifier that extends the ADC dynamic range performance. The PGA provides analog gains from 1 to 16, with gains of 32 and 64 provided by digital scaling. The PGA output signal is routed to the CAPP and CAPN pins through 270Ω resistors. Connect an external 10nF, C0G-dielectric capacitor across these pins. An antialias filter is formed by these components to attenuate the signal level at the modulator aliasing frequency (fMOD).

As shown in Figure 7-4, the buffer is used between the PGA and the modulator. Connect two 47nF, C0G-dielectric capacitors from each buffer output to AVSS (CAPBP and CAPBN). A voltage charge pump increases the buffer input voltage headroom. Connect an external 4.7nF capacitor between CAPC and AGND for charge pump operation.

The PGA gain is programmed by the GAIN[2:0] bits of the CONFIG1 register. Table 7-2 shows the PGA gain settings and buffer selection. The PGA gains and input signal range are irrespective of the voltage reference.

Table 7-2 PGA Gains
GAIN[2:0] REGISTER BITS PGA GAIN INPUT SIGNAL RANGE (VPP)
000 1 ±2.5
001 2 ±1.25
010 4 ±0.625
011 8 ±0.3125
100 16 ±0.15625
101 32 ±0.078125
110 64 ±0.0390625
111 Buffer mode, gain = 1 ±2.5

Observe the PGA input and output voltage headroom specification. Figure 7-5 shows the input and output voltage headroom when operating with AVDD1 = 5V, an input common-mode voltage (VCM) = 2.5V, a differential input voltage = ±2.5VPP, and at gain = 1. The absolute minimum and maximum PGA input voltage (1.25V and 3.75V) is ±1/2 of the differential signal voltage plus the common-mode voltage. The PGA provides 0.15V input voltage margin at the negative peak and 0.4V input voltage margin at the positive peak. As shown in the figure, the PGA gain increases by × 1.5 when the ADC is operated with 4.096V or 5V voltage references. The PGA provides 0.475V output voltage margin at the positive and negative peaks.

ADS1285 PGA Headroom (AVDD1 = 5V, PGA Gain = 1) Figure 7-5 PGA Headroom (AVDD1 = 5V, PGA Gain = 1)

When operating with AVDD1 = 3.3V, the PGA cannot support ±2.5VPP input signals. Use the buffer for ±2.5VPP input signals. For ±1.25VPP input signals (PGA gain = 2), the input headroom is increased by increasing the common-mode voltage by 0.1V to AVSS + 1.75V. Figure 7-6 illustrates the input and output operating headroom for AVDD1 = 3.3V, VCM = 1.75V, input signal = ±1.25VPP, and gain = 2. The PGA uses normal gain scaling when VREF = 2.5V.

ADS1285 PGA Headroom (AVDD1 = 3.3V, Gain = 2) Figure 7-6 PGA Headroom (AVDD1 = 3.3V, Gain = 2)