SBAS559B May   2022  – November 2025 ADS1285

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements: 1.65V ≤ IOVDD ≤ 1.95V and 2.7V ≤ IOVDD ≤ 3.6V
    7. 5.7 Switching Characteristics: 1.65V ≤ IOVDD ≤ 1.95V and 2.7V ≤ IOVDD ≤ 3.6V
    8. 5.8 Timing Diagrams
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Noise Performance
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Input
      2. 7.3.2 PGA and Buffer
        1. 7.3.2.1 Programmable Gain Amplifier (PGA)
        2. 7.3.2.2 Buffer Operation (PGA Bypass)
      3. 7.3.3 Voltage Reference Input
      4. 7.3.4 IOVDD Power Supply
      5. 7.3.5 Modulator
        1. 7.3.5.1 Modulator Overdrive
      6. 7.3.6 Digital Filter
        1. 7.3.6.1 Sinc Filter Section
        2. 7.3.6.2 FIR Filter Section
        3. 7.3.6.3 Group Delay and Step Response
          1. 7.3.6.3.1 Linear Phase Response
          2. 7.3.6.3.2 Minimum Phase Response
        4. 7.3.6.4 HPF Stage
      7. 7.3.7 Clock Input
      8. 7.3.8 GPIO
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power Modes
      2. 7.4.2 Power-Down Mode
      3. 7.4.3 Reset
      4. 7.4.4 Synchronization
        1. 7.4.4.1 Pulse-Sync Mode
        2. 7.4.4.2 Continuous-Sync Mode
      5. 7.4.5 Sample Rate Converter
      6. 7.4.6 Offset and Gain Calibration
        1. 7.4.6.1 OFFSET Register
        2. 7.4.6.2 GAIN Register
        3. 7.4.6.3 Calibration Procedure
    5. 7.5 Programming
      1. 7.5.1 Serial Interface
        1. 7.5.1.1 Chip Select (CS)
        2. 7.5.1.2 Serial Clock (SCLK)
        3. 7.5.1.3 Data Input (DIN)
        4. 7.5.1.4 Data Output (DOUT)
        5. 7.5.1.5 Data Ready (DRDY)
      2. 7.5.2 Conversion Data Format
      3. 7.5.3 Commands
        1. 7.5.3.1  Single Byte Command
        2. 7.5.3.2  WAKEUP: Wake Command
        3. 7.5.3.3  STANDBY: Software Power-Down Command
        4. 7.5.3.4  SYNC: Synchronize Command
        5. 7.5.3.5  RESET: Reset Command
        6. 7.5.3.6  Read Data Direct
        7. 7.5.3.7  RDATA: Read Conversion Data Command
        8. 7.5.3.8  RREG: Read Register Command
        9. 7.5.3.9  WREG: Write Register Command
        10. 7.5.3.10 OFSCAL: Offset Calibration Command
        11. 7.5.3.11 GANCAL: Gain Calibration Command
    6. 7.6 Register Map
      1. 7.6.1 Register Descriptions
        1. 7.6.1.1 ID/SYNC: Device ID, SYNC Register (Address = 00h) [Reset = xxxx0000b]
        2. 7.6.1.2 CONFIG0: Configuration Register 0 (Address = 01h) [Reset = 12h]
        3. 7.6.1.3 CONFIG1: Configuration Register 1 (Address = 02h) [Reset = 00h]
        4. 7.6.1.4 HPF0, HPF1: High-Pass Filter Registers (Address = 03h, 04h) [Reset = 32h, 03h]
        5. 7.6.1.5 OFFSET0, OFFSET1, OFFSET2: Offset Calibration Registers (Address = 05h, 06h, 07h) [Reset = 00h, 00h, 00h]
        6. 7.6.1.6 GAIN0, GAIN1, GAIN2: Gain Calibration Registers (Address = 08h, 09h, 0Ah) [Reset = 00h, 00h, 40h]
        7. 7.6.1.7 GPIO: Digital Input/Output Register (Address = 0Bh) [Reset = 000xx000b]
        8. 7.6.1.8 SRC0, SRC1: Sample Rate Converter Registers (Address = 0Ch, 0Dh) [Reset = 00h, 80h]
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Analog Power Supplies
      2. 8.3.2 Digital Power Supply
      3. 8.3.3 Grounds
      4. 8.3.4 Thermal Pad
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.9 Typical Characteristics

at TA = 25°C, AVDD1 = 5V, AVSS = 0V, AVDD2 = 2.5V, IOVDD = 1.8V, fCLK = 8.192MHz (4.096MHz low-power mode), VREFP = 4.096V, VREFN = 0V, PGA gain = 1, VCM = 2.5V, fDATA = 500 SPS (unless otherwise noted)

ADS1285 High-Power Mode FFT Spectrum
Shorted input, PGA gain = 1
Figure 5-9 High-Power Mode FFT Spectrum
ADS1285 High-Power Mode FFT Spectrum
Shorted input, PGA gain = 1, VREF = 2.5V, AVDD1 = 3.3V
Figure 5-11 High-Power Mode FFT Spectrum
ADS1285 High-Power Mode FFT Spectrum
fIN = 31.25Hz, VIN = –0.5 dBFS, PGA gain = 1
Figure 5-13 High-Power Mode FFT Spectrum
ADS1285 High-Power Mode FFT Spectrum
fIN = 31.25Hz, VIN = –0.5 dBFS, buffer operation
 
Figure 5-15 High-Power Mode FFT Spectrum
ADS1285 High-Power Mode FFT Spectrum
fIN = 31.25Hz, VIN = –0.5 dBFS, PGA gain = 8
Figure 5-17 High-Power Mode FFT Spectrum
ADS1285 Mid-Power Mode FFT Spectrum
Shorted input, PGA gain = 1
Figure 5-19 Mid-Power Mode FFT Spectrum
ADS1285 Mid-Power Mode FFT Spectrum
Shorted input, PGA gain = 1, VREF = 2.5V, AVDD1 = 3.3V
Figure 5-21 Mid-Power Mode FFT Spectrum
ADS1285 Mid-Power Mode FFT Spectrum
fIN = 31.25Hz, VIN = –20 dBFS, PGA gain = 1
 
Figure 5-23 Mid-Power Mode FFT Spectrum
ADS1285 Mid-Power Mode FFT Spectrum
fIN = 31.25Hz, VIN = –0.5 dBFS, PGA gain = 8
Figure 5-25 Mid-Power Mode FFT Spectrum
ADS1285 Low-Power Mode FFT Spectrum
Shorted input, PGA gain = 1
Figure 5-27 Low-Power Mode FFT Spectrum
ADS1285 Low-Power Mode FFT Spectrum
Shorted input, PGA gain = 1, VREF = 2.5V, AVDD1 = 3.3V
Figure 5-29 Low-Power Mode FFT Spectrum
ADS1285 Low-Power Mode FFT Spectrum
fIN = 31.25Hz, VIN = –20 dBFS, PGA gain = 1
 
Figure 5-31 Low-Power Mode FFT Spectrum
ADS1285 Low-Power Mode FFT Spectrum
fIN = 31.25Hz, VIN = –0.5 dBFS, PGA gain = 8
Figure 5-33 Low-Power Mode FFT Spectrum
ADS1285 Channel-to-Channel Crosstalk
AIN1 = fIN = 31.25Hz, –0.5dBFS signal, AIN2 = shorted
Figure 5-35 Channel-to-Channel Crosstalk
ADS1285 Dynamic Range vs PGA Gain
Mid-power mode
Figure 5-37 Dynamic Range vs PGA Gain
ADS1285 Offset Error Distribution
30 units
Figure 5-39 Offset Error Distribution
ADS1285 Gain Error Distribution
30 units
Figure 5-41 Gain Error Distribution
ADS1285 Gain Drift Distribution
30 units
Figure 5-43 Gain Drift Distribution
ADS1285 Gain Match Distribution
30 units
Figure 5-45 Gain Match Distribution
ADS1285 Mid-Power Mode THD vs PGA Gain
VREF = 2.5V, AVDD1 = 3.3V, fIN = 31.25Hz, VIN = –0.5 dBFS
Figure 5-47 Mid-Power Mode THD vs PGA Gain
ADS1285 High-Power Mode THD vs PGA Gain
VREF = 4.096V, AVDD1 = 5V, fIN = 31.25Hz, VIN = –0.5 dBFS
Figure 5-49 High-Power Mode THD vs PGA Gain
ADS1285 Low-Power Mode THD vs PGA Gain
VREF = 4.096V, AVDD1 = 5V, fIN = 31.25Hz, VIN = –0.5 dBFS
Figure 5-51 Low-Power Mode THD vs PGA Gain
ADS1285 Low-Power Mode THD vs Input Frequency
VREF = 4.096V, AVDD1 = 5V, fIN = 31.25Hz, VIN = –0.5 dBFS
Figure 5-53 Low-Power Mode THD vs Input Frequency
ADS1285 PGA Input Current Noise Distribution
 
Figure 5-55 PGA Input Current Noise Distribution
ADS1285 Reference Input Current vs Temperature
 
 
Figure 5-57 Reference Input Current vs Temperature
ADS1285 CMRR vs Common-Mode Input Frequency
 
 
Figure 5-59 CMRR vs Common-Mode Input Frequency
ADS1285 AVDD1 Current Distribution
30 units
Figure 5-61 AVDD1 Current Distribution
ADS1285 AVDD1 Current vs Temperature
 
 
Figure 5-63 AVDD1 Current vs Temperature
ADS1285 AVDD2 Current vs Temperature
 
Figure 5-65 AVDD2 Current vs Temperature
ADS1285 IOVDD Current vs Data Rate
 
Figure 5-67 IOVDD Current vs Data Rate
ADS1285 High-Power Mode FFT Spectrum
Shorted input, PGA gain = 8
Figure 5-10 High-Power Mode FFT Spectrum
ADS1285 High-Power Mode FFT Spectrum
RS = 1kΩ
Figure 5-12 High-Power Mode FFT Spectrum
ADS1285 High-Power Mode FFT Spectrum
fIN = 31.25Hz, VIN = –20 dBFS, PGA gain = 1
Figure 5-14 High-Power Mode FFT Spectrum
ADS1285 High-Power Mode FFT Spectrum
fIN = 31.25Hz, VIN = –0.5dBFS, PGA gain = 2, VREF = 2.5V, AVDD1 = 3.3V, 2048 data points
Figure 5-16 High-Power Mode FFT Spectrum
ADS1285 High-Power Mode FFT Spectrum
fIN = 31.25Hz, VIN = –20 dBFS, PGA gain = 8
Figure 5-18 High-Power Mode FFT Spectrum
ADS1285 Mid-Power Mode FFT Spectrum
Shorted input, PGA gain = 8
Figure 5-20 Mid-Power Mode FFT Spectrum
ADS1285 Mid-Power Mode FFT Spectrum
fIN = 31.25Hz, VIN = –0.5 dBFS, PGA gain = 1
Figure 5-22 Mid-Power Mode FFT Spectrum
ADS1285 Mid-Power Mode FFT Spectrum
fIN = 31.25Hz, VIN = –0.5dBFS, PGA gain = 2, VREF = 2.5V, AVDD1 = 3.3V, 2048 data points
Figure 5-24 Mid-Power Mode FFT Spectrum
ADS1285 Mid-Power Mode FFT Spectrum
fIN = 31.25Hz, VIN = –20 dBFS, PGA gain = 8
Figure 5-26 Mid-Power Mode FFT Spectrum
ADS1285 Low-Power Mode FFT Spectrum
Shorted input, PGA gain = 8
Figure 5-28 Low-Power Mode FFT Spectrum
ADS1285 Low-Power Mode FFT Spectrum
fIN = 31.25Hz, VIN = –0.5 dBFS, PGA gain = 1
Figure 5-30 Low-Power Mode FFT Spectrum
ADS1285 Low-Power Mode FFT Spectrum
fIN = 31.25Hz, VIN = –0.5dBFS, PGA gain = 2, VREF = 2.5V, AVDD1 = 3.3V, 2048 data points
Figure 5-32 Low-Power Mode FFT Spectrum
ADS1285 Low-Power Mode FFT Spectrum
fIN = 31.25Hz, VIN = –20 dBFS, PGA gain = 8
Figure 5-34 Low-Power Mode FFT Spectrum
ADS1285 Dynamic Range vs PGA Gain
High-power mode
Figure 5-36 Dynamic Range vs PGA Gain
ADS1285 Dynamic Range vs PGA Gain
Low-power mode
Figure 5-38 Dynamic Range vs PGA Gain
ADS1285 Offset Drift Distribution
30 units
Figure 5-40 Offset Drift Distribution
ADS1285 Gain Error Distribution
30 units
Figure 5-42 Gain Error Distribution
ADS1285 Gain Drift Distribution
30 units
Figure 5-44 Gain Drift Distribution
ADS1285 High-Power Mode THD vs PGA Gain
VREF = 2.5V, AVDD1 = 3.3V, fIN = 31.25Hz, VIN = –0.5 dBFS
Figure 5-46 High-Power Mode THD vs PGA Gain
ADS1285 Low-Power Mode THD vs PGA Gain
VREF = 2.5V, AVDD1 = 3.3V, fIN = 31.25Hz, VIN = –0.5 dBFS
Figure 5-48 Low-Power Mode THD vs PGA Gain
ADS1285 Mid-Power Mode THD vs PGA Gain
VREF = 4.096V, AVDD1 = 5V, fIN = 31.25Hz, VIN = –0.5 dBFS
Figure 5-50 Mid-Power Mode THD vs PGA Gain
ADS1285 High- and Mid-Power Mode THD vs Input Frequency
VREF = 4.096V, AVDD1 = 5V, fIN = 31.25Hz, VIN = –0.5 dBFS
Figure 5-52 High- and Mid-Power Mode THD vs Input Frequency
ADS1285 PGA Input Current vs Input Voltage
High-speed mode
Figure 5-54 PGA Input Current vs Input Voltage
ADS1285 Buffer Input Current vs Input Voltage
High- and mid-power modes
 
Figure 5-56 Buffer Input Current vs Input Voltage
ADS1285 Reference Input Current Distribution
30 units
Figure 5-58 Reference Input Current Distribution
ADS1285 AVDD1 Current Distribution
30 units
Figure 5-60 AVDD1 Current Distribution
ADS1285 AVDD1 Current vs Temperature
 
 
Figure 5-62 AVDD1 Current vs Temperature
ADS1285 AVDD2 Current Distribution
30 units
Figure 5-64 AVDD2 Current Distribution
ADS1285 PSRR vs Power-Supply Frequency
 
Figure 5-66 PSRR vs Power-Supply Frequency