The ADS8588H supports a parallel interface mode for reading the device output data using the control inputs ( CS and RD), the parallel output bus (DB[15:0]), and the BUSY indicator. This interface mode is selected by applying a logic low input on the PAR/SER/BYTE SEL input pin. Depending on the application requirements, the CS and RD control inputs can be tied together or used as separate control inputs in the parallel interface mode.

For applications that use only one device in the system and do not share the parallel output bus with any other devices, the CS and RD input signals can be tied together. Alternatively, the CS signal can be permanently tied low and the RD signal can be used to clock the data out of the device. The timing diagram for this mode of operation is described in the Timing Requirements: Parallel Data Read Operation, CS and RD Tied Together table. In this mode, the parallel output bus (DB[15:0]) is activated (comes out of tri-state) on the falling edge of the CS/ RD signal. At the first falling edge of the CS/ RD signal, the output data of channel 1 becomes available on the parallel bus to be read by the digital host. The FRSTDATA output is held high during the data readback of channel 1, indicating channel 1 data are ready to be read back. The output data for the remaining channels are clocked out on the parallel bus on subsequent falling edges of the CS and RD signal in a sequential manner. The FRSTDATA output is held low during this time period.

For applications that use multiple devices in the system, the CS and RD input signals must be driven separately. The timing diagram for this mode of operation is described in the Timing Requirements: Parallel Data Read Operation, CS and RD Separate table. A falling edge of the CS input can be used to activate the parallel bus for a particular device in the system. The RD signal clocks the conversion data out of the device. At the first falling edge of the RD signal, the output data of channel 1 become available on the parallel bus to be read by the digital host. The FRSTDATA output is held high during the data readback of channel 1, indicating channel 1 data are ready to be read back. On subsequent falling edges of the RD signal, the output data for the remaining channels are clocked out on the parallel bus in a sequential manner. At the second falling edge of the RD signal, the FRSTDATA output goes low and remains low until going to tri-state at the next rising edge of the CS signal.