The ADS8588H allows all analog input channels to be simultaneously sampled. In order to do so, the CONVSTA and CONVSTB signals must be tied together as shown in Figure 7-16 and a single CONVST signal must be used to control the sampling of all analog input channels of the device. Figure 7-16 also shows the sequence of events described in this section.

Figure 7-16 Simultaneous Sampling of All Input Channels in Parallel Interface Timing Diagram

There are four events that describe the internal operation of the device when all input channels are simultaneously sampled and the data are read back. These events are:

• Event 1: Simultaneous sampling of all analog input channels is initiated with the rising edge of the CONVST signal. The input signals on all channels are sampled at this same instant because both the CONVSTA and CONVSTB inputs are tied together. The sampled signals are then converted by the ADCs using a precise on-chip oscillator clock. At the beginning of the conversion phase of the ADC, the BUSY output goes high and remains high through a maximum-specified conversion time of t_CONV (see the Timing Requirements: CONVST ControlTiming Requirements: CONVST Control table).
• Event 2: At this instant, the ADC has completed the conversion for all input channels and the BUSY output goes to logic low. The falling edge of the BUSY signal indicates end of conversion and that the internal registers are updated with the conversion data. At this instant, the device is ready to output the correct conversion results for all channels on the parallel output bus (DB[15:0]), serial output lines (DOUTA, DOUTB), or parallel byte bus (DB[7:0]).
• Event 3: This example shows the data read operation in parallel interface mode with both CS and RD tied together. After BUSY goes low, the first falling edges of CS and RD output the conversion result of channel 1 (AIN_1) on the parallel output bus. Similarly, the conversion results for the remaining channels are output on the parallel bus on subsequent falling edges of the CS and RD signals in a sequential manner. If all channels are not used in the conversion process, tie the unused channels to AGND or any known voltage within the selected input range. The ADC always converts all analog input channels and the results for unused channels are included in the output data stream, thus all unused channels must be tied to AGND or a known voltage within the range. The FRSTDATA output goes high on the first falling edges of the CS and RD signals, indicating that the parallel bus is carrying the output result from channel 1. On the next falling edge of the CS and RD signals, FRSTDATA goes low and stays low if the CS and RD inputs are low.
• Event 4: After the conversion results for all analog channels are output from the device, the data frame can be terminated by pulling the CS and RD signals to logic high. The parallel bus and FRSTDATA output go to tri-state until the entire sequence is repeated beginning from event 1.

Events 1 and 2 are common to all interface modes of operation (parallel or serial or parallel byte).