SBOS531E August   2010  – June 2019 AFE031


  1. Features
  2. Applications
  3. Description
    1.     Device Images
  4. Revision History
  5. Description, continued
  6. Device Comparison Table
  7. Pin Configuration and Functions
    1.     Pin Functions
  8. Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Thermal Information
    4. 8.4  Electrical Characteristics: Transmitter (Tx)
    5. 8.5  Electrical Characteristics: Power Amplifier (PA)
    6. 8.6  Electrical Characteristics: Receiver (Rx)
    7. 8.7  Electrical Characteristics: Digital
    8. 8.8  Electrical Characteristics: Two-Wire Interface
    9. 8.9  Electrical Characteristics: Internal Bias Generator
    10. 8.10 Electrical Characteristics: Power Supply
    11. 8.11 Timing Requirements
    12. 8.12 Timing Diagrams
    13. 8.13 Typical Characteristics
  9. Detailed Description
    1. 9.1 Functional Block Diagram
    2. 9.2 Feature Description
      1. 9.2.1 PA Block
      2. 9.2.2 Tx Block
      3. 9.2.3 Rx Block
      4. 9.2.4 DAC Block
      5. 9.2.5 REF1 and REF2 Blocks
      6. 9.2.6 Zero Crossing Detector Block
      7. 9.2.7 ETx and ERx Blocks
    3. 9.3 Power Supplies
    4. 9.4 Pin Descriptions
      1. 9.4.1 Current Overload
      2. 9.4.2 Thermal Overload
    5. 9.5 Calibration Modes
      1. 9.5.1 Tx Calibration Mode
      2. 9.5.2 Rx Calibration Mode
    6. 9.6 Serial Interface
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Detailed Design Procedure
        1. Line-Coupling Circuit
        2. Circuit Protection
        3. Thermal Considerations
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Development Support
        1. Powerline Communications Developer’s Kit
        2. TINA-TI™ (Free Software Download)
        3. TI Precision Designs
        4. WEBENCH Filter Designer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Thermal Considerations

In a typical powerline communications application, the AFE031 dissipates 2 W of power when transmitting into the low impedance of the ac line. This amount of power dissipation can increase the junction temperature, which in turn can lead to a thermal overload that results in signal transmission interruptions if the proper thermal design of the PCB has not been performed. Proper management of heat flow from the AFE031 as well as good PCB design and construction are required to ensure proper device temperature, maximize performance, and extend device operating life.

The AFE031 is assembled into a 7-mm2 x 7-mm2, 48-lead, QFN package. As Figure 51 shows, this QFN package has a large area exposed thermal pad on the underside that is used to conduct heat away from the AFE031 and into the underlying PCB.

AFE031 ai_qfn_pkg_boa130.gifFigure 51. QFN Package with Large Area Exposed Thermal Pad

Some heat is conducted from the silicon die surface through the plastic packaging material and is transferred into the ambient environment. Because plastic is a relatively poor conductor of heat, however, this route is not the primary thermal path for heat flow. Heat also flows across the silicon die surface to the bond pads, through the wire bonds, into the package leads, and finally into the top layer of the PCB. While both of these paths for heat flow are important, the majority (nearly 80%) of the heat flows downward, through the silicon die, into the thermally-conductive die attach epoxy, and into the exposed thermal pad on the underside of the package (see Figure 52). Minimizing the thermal resistance of this downward path to the ambient environment maximizes the life and performance of the device.

AFE031 ai_qfn_heat_flow_boa130.gifFigure 52. Heat Flow in the QFN Package

The exposed thermal pad must be soldered to the PCB thermal pad. The thermal pad on the PCB should be the same size as the exposed thermal pad on the underside of the QFN package. Refer to Application Report, QFN/SON PCB Attachment, literature number SLUA271A, for recommendations on attaching the thermal pad to the PCB. Figure 53 illustrates the direction of heat spreading into the PCB from the device.

AFE031 ai_pcb_heat_flow_boa130.gifFigure 53. Heat Spreading into PCB

The heat spreading into the PCB is maximized if the thermal path is uninterrupted. Best results are achieved if the heat-spreading surfaces are filled with copper to the greatest extent possible, maximizing the percent area covered on each layer. As an example, a thermally robust, multilayer PCB design may consist of four layers with copper (Cu) coverage of 60% in the top layer, 85% and 90% in the inner layers, respectively, and 95% on the bottom layer.

Increasing the number of layers in the PCB, using thicker copper, and increasing the PCB area are all factors that improve the spread of heat. Figure 54 through Figure 56, respectively, show thermal resistance performance as a function of each of these factors.

AFE031 tc_therm_resist_pcb_layers_boa130.gifFigure 54. Thermal Resistance as a Function of the Number of Layers in the PCB
AFE031 tc_therm_resist_thickness_boa130.gifFigure 56. Thermal Resistance as a Function of Copper Thickness
AFE031 tc_therm_resist_board_area_boa130.gifFigure 55. Thermal Resistance as a Function of PCB Area

For additional information on thermal PCB design using exposed thermal pad packages, refer to Application Report Analog Front-End Design for a Narrowband Power-Line Communications Modem Using the AFE031 and Application Report PowerPAD™ Thermally-Enhanced Package; both documents available for download at