SPRSP65J April   2021  – June 2026 AM2431 , AM2432 , AM2434

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Device Comparison
    1. 4.1 Related Products
  6. 5 Terminal Configuration and Functions
    1. 5.1 Pin Diagram
      1. 5.1.1 AM243x ALV/ANI Pin Diagram
      2. 5.1.2 AM243x ALX Pin Diagram
    2. 5.2 Pin Attributes
      1.      13
      2.      14
    3. 5.3 Signal Descriptions
      1.      16
      2. 5.3.1  AM243x_ALX Package - Unsupported Interfaces and Signals
      3. 5.3.2  ADC
        1.       MAIN Domain Instances
          1.        20
      4. 5.3.3  CPSW
        1.       MAIN Domain Instances
          1.        23
          2.        24
          3.        25
          4.        26
          5. 5.3.3.1.1 CPSW3G IOSETs
      5. 5.3.4  CPTS
        1.       MAIN Domain Instances
          1.        30
          2.        31
      6. 5.3.5  DDRSS
        1.       MAIN Domain Instances
          1.        34
      7. 5.3.6  ECAP
        1.       MAIN Domain Instances
          1.        37
          2.        38
          3.        39
      8. 5.3.7  Emulation and Debug
        1.       MAIN Domain Instances
          1.        42
        2.       MCU Domain Instances
          1.        44
      9. 5.3.8  EPWM
        1.       MAIN Domain Instances
          1.        47
          2.        48
          3.        49
          4.        50
          5.        51
          6.        52
          7.        53
          8.        54
          9.        55
          10.        56
      10. 5.3.9  EQEP
        1.       MAIN Domain Instances
          1.        59
          2.        60
          3.        61
      11. 5.3.10 FSI
        1.       MAIN Domain Instances
          1.        64
          2.        65
          3.        66
          4.        67
          5.        68
          6.        69
          7.        70
          8.        71
      12. 5.3.11 GPIO
        1.       MAIN Domain Instances
          1.        74
          2.        75
        2.       MCU Domain Instances
          1.        77
      13. 5.3.12 GPMC
        1.       MAIN Domain Instances
          1.        80
          2. 5.3.12.1.1 GPMC0 IOSETs (ALV/ANI)
      14. 5.3.13 I2C
        1.       MAIN Domain Instances
          1.        84
          2.        85
          3.        86
          4.        87
        2.       MCU Domain Instances
          1.        89
          2.        90
      15. 5.3.14 MCAN
        1.       MAIN Domain Instances
          1.        93
          2.        94
      16. 5.3.15 SPI (MCSPI)
        1.       MAIN Domain Instances
          1.        97
          2.        98
          3.        99
          4.        100
          5.        101
        2.       MCU Domain Instances
          1.        103
          2.        104
      17. 5.3.16 MMC
        1.       MAIN Domain Instances
          1.        107
          2.        108
      18. 5.3.17 OSPI
        1.       MAIN Domain Instances
          1.        111
      19. 5.3.18 Power Supply
        1.       113
      20. 5.3.19 PRU_ICSSG
        1.       MAIN Domain Instances
          1.        116
          2.        117
      21. 5.3.20 Reserved and No Connect
        1.       119
      22. 5.3.21 SERDES
        1.       MAIN Domain Instances
          1.        122
      23. 5.3.22 System and Miscellaneous
        1. 5.3.22.1 Boot Mode Configuration
          1.        MAIN Domain Instances
            1.         126
        2. 5.3.22.2 Clocking
          1.        MCU Domain Instances
            1.         129
        3. 5.3.22.3 SYSTEM
          1.        MAIN Domain Instances
            1.         132
          2.        MCU Domain Instances
            1.         134
        4. 5.3.22.4 VMON
          1.        136
      24. 5.3.23 TIMER
        1.       MAIN Domain Instances
          1.        139
        2.       MCU Domain Instances
          1.        141
      25. 5.3.24 UART
        1.       MAIN Domain Instances
          1.        144
          2.        145
          3.        146
          4.        147
          5.        148
          6.        149
          7.        150
        2.       MCU Domain Instances
          1.        152
          2.        153
      26. 5.3.25 USB
        1.       MAIN Domain Instances
          1.        156
    4. 5.4 Pin Connectivity Requirements
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Power-On Hours (POH)
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Operating Performance Points
    6. 6.6  Power Consumption Summary
    7. 6.7  Electrical Characteristics
      1. 6.7.1  I2C Open-Drain, and Fail-Safe (I2C OD FS) Electrical Characteristics
      2. 6.7.2  Fail-Safe Reset (FS RESET) Electrical Characteristics
      3. 6.7.3  High-Frequency Oscillator (HFOSC) Electrical Characteristics
      4. 6.7.4  eMMCPHY Electrical Characteristics
      5. 6.7.5  SDIO Electrical Characteristics
      6. 6.7.6  LVCMOS Electrical Characteristics
      7. 6.7.7  ADC12B Electrical Characteristics (ALV/ANI package)
      8. 6.7.8  ADC10B Electrical Characteristics (ALX package)
      9. 6.7.9  USB2PHY Electrical Characteristics
      10. 6.7.10 SerDes PHY Electrical Characteristics
      11. 6.7.11 DDR Electrical Characteristics
    8. 6.8  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. 6.8.1 Recommended Operating Conditions for OTP eFuse Programming
      2. 6.8.2 Hardware Requirements
      3. 6.8.3 Programming Sequence
      4. 6.8.4 Impact to Your Hardware Warranty
    9. 6.9  Thermal Resistance Characteristics
      1. 6.9.1 Thermal Resistance Characteristics
    10. 6.10 Temperature Sensor Characteristics
    11. 6.11 Timing and Switching Characteristics
      1. 6.11.1 Timing Parameters and Information
      2. 6.11.2 Power Supply Requirements
        1. 6.11.2.1 Power Supply Slew Rate Requirement
        2. 6.11.2.2 Power Supply Sequencing
          1. 6.11.2.2.1 Power-Up Sequencing
          2. 6.11.2.2.2 Power-Down Sequencing
      3. 6.11.3 System Timing
        1. 6.11.3.1 Reset Timing
        2. 6.11.3.2 Safety Signal Timing
        3. 6.11.3.3 Clock Timing
      4. 6.11.4 Clock Specifications
        1. 6.11.4.1 Input Clocks / Oscillators
          1. 6.11.4.1.1 MCU_OSC0 Internal Oscillator Clock Source
            1. 6.11.4.1.1.1 Load Capacitance
            2. 6.11.4.1.1.2 Shunt Capacitance
          2. 6.11.4.1.2 MCU_OSC0 LVCMOS Digital Clock Source
        2. 6.11.4.2 Output Clocks
        3. 6.11.4.3 PLLs
        4. 6.11.4.4 Recommended System Precautions for Clock and Control Signal Transitions
      5. 6.11.5 Peripherals
        1. 6.11.5.1  CPSW3G
          1. 6.11.5.1.1 CPSW3G MDIO Timing
          2. 6.11.5.1.2 CPSW3G RMII Timing
          3. 6.11.5.1.3 CPSW3G RGMII Timing
          4. 6.11.5.1.4 CPSW3G IOSETs
        2. 6.11.5.2  DDRSS
        3. 6.11.5.3  ECAP
        4. 6.11.5.4  EPWM
        5. 6.11.5.5  EQEP
        6. 6.11.5.6  FSI
        7. 6.11.5.7  GPIO
        8. 6.11.5.8  GPMC
          1. 6.11.5.8.1 GPMC and NOR Flash — Synchronous Mode
          2. 6.11.5.8.2 GPMC and NOR Flash — Asynchronous Mode
          3. 6.11.5.8.3 GPMC and NAND Flash — Asynchronous Mode
          4. 6.11.5.8.4 GPMC0 IOSETs (ALV/ANI)
        9. 6.11.5.9  I2C
        10. 6.11.5.10 MCAN
        11. 6.11.5.11 MCSPI
          1. 6.11.5.11.1 MCSPI — Controller Mode
          2. 6.11.5.11.2 MCSPI — Peripheral Mode
        12. 6.11.5.12 MMCSD
          1. 6.11.5.12.1 MMC0 - eMMC Interface
            1. 6.11.5.12.1.1 Legacy SDR Mode
            2. 6.11.5.12.1.2 High Speed SDR Mode
            3. 6.11.5.12.1.3 High Speed DDR Mode
            4. 6.11.5.12.1.4 HS200 Mode
          2. 6.11.5.12.2 MMC1 - SD/SDIO Interface
            1. 6.11.5.12.2.1 Default Speed Mode
            2. 6.11.5.12.2.2 High Speed Mode
            3. 6.11.5.12.2.3 UHS–I SDR12 Mode
            4. 6.11.5.12.2.4 UHS–I SDR25 Mode
            5. 6.11.5.12.2.5 UHS–I SDR50 Mode
            6. 6.11.5.12.2.6 UHS–I DDR50 Mode
            7. 6.11.5.12.2.7 UHS–I SDR104 Mode
        13. 6.11.5.13 CPTS
        14. 6.11.5.14 OSPI
          1. 6.11.5.14.1 OSPI0 PHY Mode
            1. 6.11.5.14.1.1 OSPI0 With PHY Data Training
            2. 6.11.5.14.1.2 OSPI0 Without Data Training
              1. 6.11.5.14.1.2.1 OSPI0 PHY SDR Timing
              2. 6.11.5.14.1.2.2 OSPI0 PHY DDR Timing
          2. 6.11.5.14.2 OSPI0 Tap Mode
            1. 6.11.5.14.2.1 OSPI0 Tap SDR Timing
            2. 6.11.5.14.2.2 OSPI0 Tap DDR Timing
        15. 6.11.5.15 PCIe
        16. 6.11.5.16 PRU_ICSSG
          1. 6.11.5.16.1 PRU_ICSSG Programmable Real-Time Unit (PRU)
            1. 6.11.5.16.1.1 PRU_ICSSG PRU Direct Output Mode Timing
            2. 6.11.5.16.1.2 PRU_ICSSG PRU Parallel Capture Mode Timing
            3. 6.11.5.16.1.3 PRU_ICSSG PRU Shift Mode Timing
            4. 6.11.5.16.1.4 PRU_ICSSG PRU Sigma Delta and Peripheral Interface
              1. 6.11.5.16.1.4.1 PRU_ICSSG PRU Sigma Delta and Peripheral Interface Timing
          2. 6.11.5.16.2 PRU_ICSSG Pulse Width Modulation (PWM)
            1. 6.11.5.16.2.1 PRU_ICSSG PWM Timing
          3. 6.11.5.16.3 PRU_ICSSG Industrial Ethernet Peripheral (IEP)
            1. 6.11.5.16.3.1 PRU_ICSSG IEP Timing
          4. 6.11.5.16.4 PRU_ICSSG Universal Asynchronous Receiver Transmitter (UART)
            1. 6.11.5.16.4.1 PRU_ICSSG UART Timing
          5. 6.11.5.16.5 PRU_ICSSG Enhanced Capture Peripheral (ECAP)
            1. 6.11.5.16.5.1 PRU_ICSSG ECAP Timing
          6. 6.11.5.16.6 PRU_ICSSG RGMII, MII_RT, and Switch
            1. 6.11.5.16.6.1 PRU_ICSSG MDIO Timing
            2. 6.11.5.16.6.2 PRU_ICSSG MII Timing
            3. 6.11.5.16.6.3 PRU_ICSSG RGMII Timing
        17. 6.11.5.17 Timers
        18. 6.11.5.18 UART
        19. 6.11.5.19 USB
      6. 6.11.6 Emulation and Debug
        1. 6.11.6.1 Trace
        2. 6.11.6.2 JTAG
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Processor Subsystems
      1. 7.2.1 Arm Cortex-R5F Subsystem (R5FSS)
      2. 7.2.2 Arm Cortex-M4F (M4FSS)
    3. 7.3 Accelerators and Coprocessors
      1. 7.3.1 Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU_ICSSG)
    4. 7.4 Other Subsystems
      1. 7.4.1 PDMA Controller
      2. 7.4.2 Peripherals
        1. 7.4.2.1  ADC
        2. 7.4.2.2  DCC
        3. 7.4.2.3  Dual Date Rate (DDR) External Memory Interface (DDRSS)
        4. 7.4.2.4  ECAP
        5. 7.4.2.5  EPWM
        6. 7.4.2.6  ELM
        7. 7.4.2.7  ESM
        8. 7.4.2.8  GPIO
        9. 7.4.2.9  EQEP
        10. 7.4.2.10 General-Purpose Memory Controller (GPMC)
        11. 7.4.2.11 I2C
        12. 7.4.2.12 MCAN
        13. 7.4.2.13 MCRC Controller
        14. 7.4.2.14 MCSPI
        15. 7.4.2.15 MMCSD
        16. 7.4.2.16 OSPI
        17. 7.4.2.17 Peripheral Component Interconnect Express (PCIe)
        18. 7.4.2.18 Serializer/Deserializer (SerDes) PHY
        19. 7.4.2.19 Real Time Interrupt (RTI/WWDT)
        20. 7.4.2.20 Dual Mode Timer (DMTIMER)
        21. 7.4.2.21 UART
        22. 7.4.2.22 Universal Serial Bus Subsystem (USBSS)
  9. 8 Applications, Implementation, and Layout
    1. 8.1 Device Connection and Layout Fundamentals
      1. 8.1.1 Power Supply
        1. 8.1.1.1 Power Supply Designs
        2. 8.1.1.2 Power Distribution Network Implementation Guidance
      2. 8.1.2 External Oscillator
      3. 8.1.3 JTAG, EMU, and TRACE
      4. 8.1.4 Unused Pins
    2. 8.2 Peripheral- and Interface-Specific Design Information
      1. 8.2.1 General Routing Guidelines
      2. 8.2.2 DDR Board Design and Layout Guidelines
      3. 8.2.3 OSPI/QSPI/SPI Board Design and Layout Guidelines
        1. 8.2.3.1 No Loopback, Internal PHY Loopback, and Internal Pad Loopback
        2. 8.2.3.2 External Board Loopback
        3. 8.2.3.3 DQS (only available in Octal SPI devices)
      4. 8.2.4 USB VBUS Design Guidelines
      5. 8.2.5 System Power Supply Monitor Design Guidelines
      6. 8.2.6 High Speed Differential Signal Routing Guidance
      7. 8.2.7 Thermal Solution Guidance
    3. 8.3 Clock Routing Guidelines
      1. 8.3.1 Oscillator Routing
      2. 8.3.2 Oscillator Ground Connection
  10. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
      1. 9.1.1 Standard Package Symbolization
      2. 9.1.2 Device Naming Convention
    2. 9.2 Tools and Software
    3. 9.3 Documentation Support
      1. 9.3.1 Information About Cautions and Warnings
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ALV|441
  • ANI|441
  • ALX|293
Thermal pad, mechanical data (Package|Pins)
Orderable Information
Table 5-3 ADC0 Signal Descriptions
SIGNAL NAME [1]SIGNAL
TYPE [2]		DESCRIPTION [3]ALV/ANI PIN [4]ALX PIN [4]
ADC0_REFN (5) (7)AADC0 Negative ReferenceJ16
ADC0_REFP (5) (6)AADC0 Positive ReferenceJ15
ADC0_AIN0 (2) (3) (4)AADC Analog Input 0 / GPIO1_80 (Input Only)G20H21
ADC0_AIN1 (2) (3) (4)AADC Analog Input 1 / GPIO1_81 (Input Only)F20F19
ADC0_AIN2 (2) (3) (4)AADC Analog Input 2 / GPIO1_82 (Input Only)E21F21
ADC0_AIN3 (2) (3) (4)AADC Analog Input 3 / GPIO1_83 (Input Only)D20F20
ADC0_AIN4 (2) (3) (4)AADC Analog Input 4 / GPIO1_84 (Input Only)G21H20
ADC0_AIN5 (2) (3) (4)AADC Analog Input 5 / GPIO1_85 (Input Only)F21E21
ADC0_AIN6 (2) (3) (4)AADC Analog Input 6 / GPIO1_86 (Input Only)F19G20
ADC0_AIN7 (2) (3) (4)AADC Analog Input 7 / GPIO1_87 (Input Only)E20E20
ADC_EXT_TRIGGER0 (1)IADC Trigger InputB16, C13B7, B9
ADC_EXT_TRIGGER1 (1)IADC Trigger InputD14, D16C11
(1) This ADC Trigger input signal has a debounce function. For more information on I/O Debounce configuration, see the TRM Device Configuration chapter.
(2) The General Purpose Input signal associated with this ADC0_AIN input has a debounce function when ADC0 is configured to operate in GPI mode. For more information on configuring ADC0 to operate in GPI mode, see the TRM Analog-to-Digital Converter (ADC) section in the Peripherals chapter. For more information on I/O Debounce configuration, see the TRM Device Configuration chapter.
(3) The ADC0_AIN[7:0] inputs only have hysterisis when ADC0 is configured to operate in GPI mode.
(4) Any unused ADC0_AIN inputs must be pulled to VSS through a resistor or connected directly to VSS when VDDA_ADC is connected to a power source.
(5) The ADC0_REFP and ADC0_REFN reference inputs are analog inputs which must be treated like high transient power supply rails, where ADC0_REFN is expected to be connected directly to the PCB ground plane along with all other VSS pins, and ADC0_REFP is connected to a power source capable of providing at least 4mA of current. ADC0_REFP may be connected to the same power source as VDDA_ADC0 if the voltage tolerance of the supply provides an acceptable accuracy for the ADC reference. A high frequency decoupling capacitor must be connected directly between ADC0_REFP and ADC0_REFN. The high frequency decoupling capacitor should be placed in the ball array on the back side of the PCB and connected directly to the ADC0_REFP and ADC0_REFN pins with vias. ADC0_REFP may be connected to VSS if ADC0 is not used and VDDA_ADC0 has been connected to VSS. The high frequency decoupling capacitor described above will not be required if ADC0 is not used and ADC0_REFP is connected to VSS. See the Pin Connectivity Requirements section for more information on ADC0 connectivity.
(6) ADC0_REFP is connected to VDDA_ADC0 inside the ALX packaged devices.
(7) ADC0_REFN is connected to VSS inside the ALX packaged devices.