Table 5-115 Timing Requirements for GMAC RGMIIn Input Receive for 10/100/1000 Mbps (1)
||Setup time, receive selected signals valid before rgmiin_rxc high/low
||Hold time, receive selected signals valid after rgmiin_rxc high/low
- For RGMII, receive selected signals include: rgmiin_rxd[3:0] and rgmiin_rxctl.
A. rgmiin_rxc must be externally delayed relative to the data and control pins.
B. Data and control information is received using both edges of the clocks. rgmiin_rxd[3:0] carries data bits 3-0 on the rising edge of rgmiin_rxc and data bits 7-4 on the falling edge ofrgmiin_rxc. Similarly, rgmiin_rxctl carries RXDV on rising edge of rgmiin_rxc and RXERR on falling edge of rgmiin_rxc.Figure 5-75 GMAC Receive Interface Timing, RGMIIn Operation
Table 5-116, Table 5-117, and Figure 5-76 present switching characteristics for transmit - RGMIIn for 10/100/1000 Mbit/s.