SBASAZ3 October 2025 AMC0306M25-Q1
PRODMIX
Refer to the PDF data sheet for device specific package drawings
Figure 7-2 conceptualizes the second-order, switched-capacitor, feed-forward ΔΣ modulator implemented in the AMC0x06M25-Q1. The output V5 of the 1-bit, digital-to-analog converter (DAC) is subtracted from the input voltage VIN = (VINP – VINN). This subtraction provides an analog voltage V1 at the input of the first integrator stage. The output of the first integrator feeds the input of the second integrator stage. The result of the second integration is an output voltage V3 that is summed with VIN and the V2 output. VIN is the input signal and V2 is the first integrator. Depending on the value of the resulting voltage V4, the output of the comparator is changed. In this case, the 1-bit DAC responds on the next clock pulse by changing the associated analog output voltage V5. Thus, causing the integrators to progress in the opposite direction and forcing the integrator output value to track the average value of the input.
For reduced offset and offset drift, the integrators are chopper-stabilized with the chopping frequency set at fCLKIN / 16. Figure 7-3 shows the spur at 1.25MHz that is generated by the chopping frequency for a modulator clock of 20MHz.
| sinc3 filter, OSR = 1, fCLKIN = 20MHz, fIN = 1kHz |