SBOS948F February   2019  – May 2021 BUF634A

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics: Wide-Bandwidth Mode
    6. 7.6 Electrical Characteristics: Low-Quiescent Current Mode
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Output Current
      2. 8.3.2 Thermal Shutdown
      3. 8.3.3 ESD Protection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Adjustable Bandwidth
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 High-Frequency Applications
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power Dissipation and Thermal Considerations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 SOIC Layout Guidelines (D Package Without a Thermal Pad)
      2. 11.1.2 HSOIC Layout Guidelines (DDA Package With a Thermal Pad)
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
      2. 12.1.2 Development Support
        1. 12.1.2.1 TINA-TI (Free Software Download)
        2. 12.1.2.2 TI Precision Designs
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|8
  • DDA|8
  • DRB|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.2.2 Detailed Design Procedure

To assure that the composite amplifier remains stable, the phase shift of the BUF634A must remain small throughout the loop gain of the circuit. For a G = +1 op-amp circuit, the BUF634A must contribute little additional phase shift (approximately 20° or less) at the unity-gain frequency of the op amp. Phase shift is affected by various operating conditions that can affect the stability of the op amp.

For the circuit in Figure 9-7, most general-purpose or precision op amps remain unity-gain stable with the BUF634A connected inside the feedback loop. Large capacitive loads may require the BUF634A to be connected for wide bandwidth for stable operation. High-speed or fast-settling op amps generally require wide-bandwidth mode to remain stable and to assure good dynamic performance. Check for oscillations or excessive ringing on signal pulses with the intended load and worst-case conditions that affect phase response of the buffer to determine stability with an op amp. Connect the circuit as shown in Figure 9-7. Choose resistors to provide a voltage gain of 2 V/V. Select the feedback resistor to be 1 kΩ. Choose the input resistor to be 1 kΩ and C1 to be 10 pF. Figure 9-8 and Figure 9-9 illustrate the THD+N plots for the BUF634A used with the OPA2810 in a gain of
2-V/V composite loop. The THD+N performance is superior in a composite loop when compared with a standalone BUF634A because of the negative feedback and open-loop gain of the OPA2810. In Figure 9-8, the signal distortion degrades for large output voltages with 16-Ω and 32-Ω loads because of the device internal short-circuit protection.