SWRS205D March 2017 – September 2020 CC3120MOD
Refer to the PDF data sheet for device specific package drawings
Figure 8-7 shows the timing diagram for wakeup from HIBERNATE mode.
The internal 32.768-kHz XTAL is kept enabled by default when the chip goes into HIBERNATE mode in response to nHIB being pulled low.
Table 8-3 describes the timing requirements for nHIB.
|Thib_min||Minimum hibernate time||Minimum pulse width of nHIB being low(1)||10||ms|
|Twake_from_hib||Hardware wakeup time plus firmware initialization time||See(2)||50||ms|