SWRS226B February   2020  – May 2021 CC3230S , CC3230SF

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Functional Block Diagrams
  5. 5 Revision History
  6. 6 Device Comparison
    1. 6.1 Related Products
  7. 7 Terminal Configuration and Functions
    1. 7.1 Pin Diagram
    2. 7.2 Pin Attributes
      1. 7.2.1 Pin Descriptions
    3. 7.3 Signal Descriptions
      1.      13
    4. 7.4 Pin Multiplexing
    5. 7.5 Drive Strength and Reset States for Analog and Digital Multiplexed Pins
    6. 7.6 Pad State After Application of Power to Device, Before Reset Release
    7. 7.7 Connections for Unused Pins
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Power-On Hours (POH)
    4. 8.4  Recommended Operating Conditions
    5. 8.5  Current Consumption Summary (CC3230S)
      1.      24
    6. 8.6  Current Consumption Summary (CC3230SF)
      1.      26
    7. 8.7  TX Power Control
    8. 8.8  Brownout and Blackout Conditions
    9. 8.9  Electrical Characteristics for GPIO Pins
      1. 8.9.1 Electrical Characteristics: GPIO Pins Except 29, 30, 50, 52, and 53
      2. 8.9.2 Electrical Characteristics: GPIO Pins 29, 30, 50, 52, and 53
    10. 8.10 Electrical Characteristics for Pin Internal Pullup and Pulldown
      1.      33
    11. 8.11 WLAN Receiver Characteristics
      1.      35
    12. 8.12 WLAN Transmitter Characteristics
      1.      37
    13. 8.13 WLAN Transmitter Out-of-Band Emissions
      1. 8.13.1 WLAN Filter Requirements
    14. 8.14 BLE/2.4 GHz Radio Coexistence and WLAN Coexistence Requirements
    15. 8.15 Thermal Resistance Characteristics for RGK Package
    16. 8.16 Timing and Switching Characteristics
      1. 8.16.1 Power Supply Sequencing
      2. 8.16.2 Device Reset
      3. 8.16.3 Reset Timing
        1. 8.16.3.1 nRESET (32-kHz Crystal)
        2. 8.16.3.2 First-Time Power-Up and Reset Removal Timing Requirements (32-kHz Crystal)
        3. 8.16.3.3 nRESET (External 32-kHz Clock)
          1. 8.16.3.3.1 First-Time Power-Up and Reset Removal Timing Requirements (External 32-kHz Clock)
      4. 8.16.4 Wakeup From HIBERNATE Mode
      5. 8.16.5 Clock Specifications
        1. 8.16.5.1 Slow Clock Using Internal Oscillator
        2. 8.16.5.2 Slow Clock Using an External Clock
          1. 8.16.5.2.1 External RTC Digital Clock Requirements
        3. 8.16.5.3 Fast Clock (Fref) Using an External Crystal
          1. 8.16.5.3.1 WLAN Fast-Clock Crystal Requirements
        4. 8.16.5.4 Fast Clock (Fref) Using an External Oscillator
          1. 8.16.5.4.1 External Fref Clock Requirements (–40°C to +85°C)
      6. 8.16.6 Peripherals Timing
        1. 8.16.6.1  SPI
          1. 8.16.6.1.1 SPI Master
            1. 8.16.6.1.1.1 SPI Master Timing Parameters
          2. 8.16.6.1.2 SPI Slave
            1. 8.16.6.1.2.1 SPI Slave Timing Parameters
        2. 8.16.6.2  I2S
          1. 8.16.6.2.1 I2S Transmit Mode
            1. 8.16.6.2.1.1 I2S Transmit Mode Timing Parameters
          2. 8.16.6.2.2 I2S Receive Mode
            1. 8.16.6.2.2.1 I2S Receive Mode Timing Parameters
        3. 8.16.6.3  GPIOs
          1. 8.16.6.3.1 GPIO Output Transition Time Parameters (Vsupply = 3.3 V)
            1. 8.16.6.3.1.1 GPIO Output Transition Times (Vsupply = 3.3 V) (1) (1)
          2. 8.16.6.3.2 GPIO Input Transition Time Parameters
            1. 8.16.6.3.2.1 GPIO Input Transition Time Parameters
        4. 8.16.6.4  I2C
          1. 8.16.6.4.1 I2C Timing Parameters (1)
        5. 8.16.6.5  IEEE 1149.1 JTAG
          1. 8.16.6.5.1 JTAG Timing Parameters
        6. 8.16.6.6  ADC
          1. 8.16.6.6.1 ADC Electrical Specifications
        7. 8.16.6.7  Camera Parallel Port
          1. 8.16.6.7.1 Camera Parallel Port Timing Parameters
        8. 8.16.6.8  UART
        9. 8.16.6.9  SD Host
        10. 8.16.6.10 Timers
  9. 9 Detailed Description
    1. 9.1  Overview
    2. 9.2  Arm® Cortex®-M4 Processor Core Subsystem
    3. 9.3  Wi-Fi® Network Processor Subsystem
      1. 9.3.1 WLAN
      2. 9.3.2 Network Stack
    4. 9.4  Security
    5. 9.5  Power-Management Subsystem
    6. 9.6  Low-Power Operating Mode
    7. 9.7  Memory
      1. 9.7.1 External Memory Requirements
      2. 9.7.2 Internal Memory
        1. 9.7.2.1 SRAM
        2. 9.7.2.2 ROM
        3. 9.7.2.3 Flash Memory
        4. 9.7.2.4 Memory Map
    8. 9.8  Restoring Factory Default Configuration
    9. 9.9  Boot Modes
      1. 9.9.1 Boot Mode List
    10. 9.10 Hostless Mode
  10. 10Applications, Implementation, and Layout
    1. 10.1 Application Information
      1. 10.1.1 BLE/2.4 GHz Radio Coexistence
      2. 10.1.2 Antenna Selection
      3. 10.1.3 Typical Application
    2. 10.2 PCB Layout Guidelines
      1. 10.2.1 General PCB Guidelines
      2. 10.2.2 Power Layout and Routing
        1. 10.2.2.1 Design Considerations
      3. 10.2.3 Clock Interface Guidelines
      4. 10.2.4 Digital Input and Output Guidelines
      5. 10.2.5 RF Interface Guidelines
  11. 11Device and Documentation Support
    1. 11.1 Third-Party Products Disclaimer
    2. 11.2 Tools and Software
    3. 11.3 Firmware Updates
    4. 11.4 Device Nomenclature
    5. 11.5 Documentation Support
    6. 11.6 Support Resources
    7. 11.7 Trademarks
    8. 11.8 Electrostatic Discharge Caution
    9. 11.9 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
      1. 12.1.1 Packaging Information
      2. 12.1.2 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Table 8-1 Current Consumption Summary (CC3230S) TA = 25°C, VBAT = 3.6 V
PARAMETER TEST CONDITIONS(1)(5) MIN TYP(6) MAX UNIT
MCU ACTIVE NWP ACTIVE TX 1 DSSS TX power level = 0 272 mA
TX power level = 4 190
6 OFDM TX power level = 0 248
TX power level = 4 182
54 OFDM TX power level = 0 223
TX power level = 4 160
RX 1 DSSS 59
54 OFDM 59
NWP idle connected(3) 15.3
MCU SLEEP NWP ACTIVE TX 1 DSSS TX power level = 0 269 mA
TX power level = 4 187
6 OFDM TX power level = 0 245
TX power level = 4 179
54 OFDM TX power level = 0 220
TX power level = 4 157
RX 1 DSSS 56
54 OFDM 56
NWP idle connected(3) 12.2
MCU LPDS NWP ACTIVE TX 1 DSSS TX power level = 0 266 mA
TX power level = 4 184
6 OFDM TX power level = 0 242
TX power level = 4 176
54 OFDM TX power level = 0 217
TX power level = 4 154
RX 1 DSSS 53
54 OFDM 53
NWP LPDS(2) 120 µA at 64KB
135 µA at 256KB		 135 µA
NWP idle connected(3) 710
MCU SHUTDOWN MCU shutdown 1 µA
MCU HIBERNATE MCU hibernate 4.5 µA
Peak calibration current(4) VBAT = 3.6 V 420 mA
VBAT = 3.3 V 450
VBAT = 2.1 V 670
(1) TX power level = 0 implies maximum power (see Figure 8-1, Figure 8-2, and Figure 8-3). TX power level = 4 implies output power backed off approximately 4 dB.
(2) LPDS current does not include the external serial flash. The LPDS number of reported is with retention of 256KB of MCU SRAM. The CC3230x device can be configured to retain 0KB, 64KB, 128KB, 192KB, or 256KB of SRAM in LPDS. Each 64-KB block of MCU retained SRAM increases LPDS current by 4 µA.
(3) DTIM = 1
(4) The complete calibration can take up to 17 mJ of energy from the battery over a time of 24 ms. In default mode, calibration is performed sparingly, and typically occurs when re-enabling the NWP and when the temperature has changed by more than 20°C. There are two additional calibration modes that may be used to reduced or completely eliminate the calibration event. For further details, see CC31xx, CC32xx SimpleLink™ Wi-Fi® and IoT Network Processor Programmer's Guide.
(5) The CC3230x system is a constant power-source system. The active current numbers scale based on the VBAT voltage supplied.
(6) Typical numbers assume a VSWR of 1.5:1.