SNAS852 june   2023 CDCE6214Q1TM

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Description (cont.)
  7. 6 Device Comparison
  8. 7 Pin Configuration and Functions
  9. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Thermal Information
    5. 8.5  EEPROM Characteristics
    6. 8.6  Reference Input, Single-Ended Characteristics
    7. 8.7  Reference Input, Differential Characteristics
    8. 8.8  Reference Input, Crystal Mode Characteristics
    9. 8.9  General-Purpose Input Characteristics
    10. 8.10 Triple Level Input Characteristics
    11. 8.11 Logic Output Characteristics
    12. 8.12 Phase Locked Loop Characteristics
    13. 8.13 Closed-Loop Output Jitter Characteristics
    14. 8.14 Input and Output Isolation
    15. 8.15 Buffer Mode Characteristics
    16. 8.16 PCIe Spread Spectrum Generator
    17. 8.17 LVCMOS Output Characteristics
    18. 8.18 LP-HCSL Output Characteristics
    19. 8.19 LVDS Output Characteristics
    20. 8.20 Output Synchronization Characteristics
    21. 8.21 Power-On Reset Characteristics
    22. 8.22 I2C-Compatible Serial Interface Characteristics
    23. 8.23 Timing Requirements, I2C-Compatible Serial Interface
    24. 8.24 Power Supply Characteristics
    25. 8.25 Typical Characteristics
  10. 9 Parameter Measurement Information
    1. 9.1 Reference Inputs
    2. 9.2 Outputs
    3. 9.3 Serial Interface
    4. 9.4 PSNR Test
    5. 9.5 Clock Interfacing and Termination
      1. 9.5.1 Reference Input
      2. 9.5.2 Outputs
  11. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1 Reference Block
        1. 10.3.1.1 Zero Delay Mode, Internal and External Path
      2. 10.3.2 Phase-Locked Loop (PLL)
        1. 10.3.2.1 PLL Configuration and Divider Settings
        2. 10.3.2.2 Spread Spectrum Clocking
        3. 10.3.2.3 Digitally-Controlled Oscillator and Frequency Increment or Decrement - Serial Interface Mode and GPIO Mode
      3. 10.3.3 Clock Distribution
        1. 10.3.3.1 Glitchless Operation
        2. 10.3.3.2 Divider Synchronization
        3. 10.3.3.3 Global and Individual Output Enable
      4. 10.3.4 Power Supplies and Power Management
      5. 10.3.5 Control Pins
    4. 10.4 Device Functional Modes
      1. 10.4.1 Operation Modes
        1. 10.4.1.1 Fall-Back Mode
        2. 10.4.1.2 Pin Mode
        3. 10.4.1.3 Serial Interface Mode
    5. 10.5 Programming
      1. 10.5.1 I2C Serial Interface
      2. 10.5.2 EEPROM
        1. 10.5.2.1 EEPROM - Cyclic Redundancy Check
        2. 10.5.2.2 Recommended Programming Procedure
        3. 10.5.2.3 EEPROM Access
          1. 10.5.2.3.1 Register Commit Flow
          2. 10.5.2.3.2 Direct Access Flow
        4. 10.5.2.4 Register Bits to EEPROM Mapping
  12. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Application
      1. 11.2.1 Design Requirements
      2. 11.2.2 Detailed Design Procedure
      3. 11.2.3 Application Curves
    3. 11.3 Power Supply Recommendations
      1. 11.3.1 Power-Up Sequence
      2. 11.3.2 Decoupling
    4. 11.4 Layout
      1. 11.4.1 Layout Guidelines
      2. 11.4.2 Layout Examples
  13. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
      2. 12.1.2 Device Nomenclature
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10.3.5 Control Pins

The ultra-low power clock generator is controlled by multiple LVCMOS input pins.

The HW_SW_CTRL pin acts as an EEPROM page select. The CDCE6214Q1TM clock generator contains two pages of configuration settings. The level of this pin is sampled after device power up. A low level selects page zero. A high level selects page one. The HW_SW_CTRL pin is a tri-level input pin. This third voltage level is automatically applied by an internal voltage divider. The mid-level is used to select an internal default where the serial interface is enabled.

The PDN/SYNCN (pin 8) , SCL (pin 12), and SDA (pin 19) have a secondary functionality and can act as general-purpose inputs and outputs (GPIO). This means that either the serial interface or the GPIO functionality can be active.

The PDN/SYNCN resets the internal circuitry and is used in the initial power-up sequence. The pin can be reconfigured to act as synchronization input. The differential outputs are kept in mute while SYNCN is low. When SYNCN is high, outputs are active.

Table 10-16 Control and GPIO Pins
PIN NO.NAMETYPE2-LEVEL INPUT3-LEVEL INPUTOUTPUTTERMINATION
23HW_SW_CTRLInput-Yes-PUPD
20GPIO1Input/OutputYes-Yes-
19GPIO2Input/OutputYes-YesOpen-Drain I/O in I2C mode, CMOS (Input)
12GPIO3InputYes---
11GPIO4Input/OutputYes-Yes-
8PDNInputYes--PU (when Input)
4REFSELInput-Yes-PUPD
Table 10-17 GPIO Input and Output Signal List
ABBREVIATIONTYPEDESCRIPTION
FREQ_INCInputFrequency Increment; Increments the MASH numerator
FREQ_DECInputFrequency Decrement; Decrements the MASH numerator
OE (global)InputEnables or disables all differential outputs Y[4:1] (bypass not affected), active low.
SSC_ENInputEnables or disables SSC.
OE1InputEnables or disables OUT1, active low.
OE2InputEnables or disables OUT2, active low.
OE3InputEnables or disables OUT3, active low.
OE4InputEnables or disables OUT4, active low.
PLL_LOCKOutputPLL Lock Status. 0 = PLL out of lock; 1 = indicates PLL in lock