SNAS852 june   2023 CDCE6214Q1TM

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Description (cont.)
  7. 6 Device Comparison
  8. 7 Pin Configuration and Functions
  9. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Thermal Information
    5. 8.5  EEPROM Characteristics
    6. 8.6  Reference Input, Single-Ended Characteristics
    7. 8.7  Reference Input, Differential Characteristics
    8. 8.8  Reference Input, Crystal Mode Characteristics
    9. 8.9  General-Purpose Input Characteristics
    10. 8.10 Triple Level Input Characteristics
    11. 8.11 Logic Output Characteristics
    12. 8.12 Phase Locked Loop Characteristics
    13. 8.13 Closed-Loop Output Jitter Characteristics
    14. 8.14 Input and Output Isolation
    15. 8.15 Buffer Mode Characteristics
    16. 8.16 PCIe Spread Spectrum Generator
    17. 8.17 LVCMOS Output Characteristics
    18. 8.18 LP-HCSL Output Characteristics
    19. 8.19 LVDS Output Characteristics
    20. 8.20 Output Synchronization Characteristics
    21. 8.21 Power-On Reset Characteristics
    22. 8.22 I2C-Compatible Serial Interface Characteristics
    23. 8.23 Timing Requirements, I2C-Compatible Serial Interface
    24. 8.24 Power Supply Characteristics
    25. 8.25 Typical Characteristics
  10. 9 Parameter Measurement Information
    1. 9.1 Reference Inputs
    2. 9.2 Outputs
    3. 9.3 Serial Interface
    4. 9.4 PSNR Test
    5. 9.5 Clock Interfacing and Termination
      1. 9.5.1 Reference Input
      2. 9.5.2 Outputs
  11. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1 Reference Block
        1. 10.3.1.1 Zero Delay Mode, Internal and External Path
      2. 10.3.2 Phase-Locked Loop (PLL)
        1. 10.3.2.1 PLL Configuration and Divider Settings
        2. 10.3.2.2 Spread Spectrum Clocking
        3. 10.3.2.3 Digitally-Controlled Oscillator and Frequency Increment or Decrement - Serial Interface Mode and GPIO Mode
      3. 10.3.3 Clock Distribution
        1. 10.3.3.1 Glitchless Operation
        2. 10.3.3.2 Divider Synchronization
        3. 10.3.3.3 Global and Individual Output Enable
      4. 10.3.4 Power Supplies and Power Management
      5. 10.3.5 Control Pins
    4. 10.4 Device Functional Modes
      1. 10.4.1 Operation Modes
        1. 10.4.1.1 Fall-Back Mode
        2. 10.4.1.2 Pin Mode
        3. 10.4.1.3 Serial Interface Mode
    5. 10.5 Programming
      1. 10.5.1 I2C Serial Interface
      2. 10.5.2 EEPROM
        1. 10.5.2.1 EEPROM - Cyclic Redundancy Check
        2. 10.5.2.2 Recommended Programming Procedure
        3. 10.5.2.3 EEPROM Access
          1. 10.5.2.3.1 Register Commit Flow
          2. 10.5.2.3.2 Direct Access Flow
        4. 10.5.2.4 Register Bits to EEPROM Mapping
  12. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Application
      1. 11.2.1 Design Requirements
      2. 11.2.2 Detailed Design Procedure
      3. 11.2.3 Application Curves
    3. 11.3 Power Supply Recommendations
      1. 11.3.1 Power-Up Sequence
      2. 11.3.2 Decoupling
    4. 11.4 Layout
      1. 11.4.1 Layout Guidelines
      2. 11.4.2 Layout Examples
  13. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
      2. 12.1.2 Device Nomenclature
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10.3.3.3 Global and Individual Output Enable

The output enable functionality allows the user to enable or disable all or a specific output buffer. The bypass copy on OUT0 is excluded from the global output enable signal. When an output is disabled, the signal drives a configurable mute-state. When the serial interface is deactivated, one can use all individual output enable signals at the same time. The individual output enable signal controls the respective output channel integer divider to gate the clock, therefore each integer divider must be active.

The individual output enable signal enables and disables the respective output in a deterministic way. Therefore the high and low level of the signal is qualified by counting four cycles of the respective output clock.

Table 10-14 Glitchless Operation and Divider Synchronization
REGISTER BIT ADDRESSREGISTER BIT FIELD NAMEDESCRIPTION
R0[14]PDN_INPUT_SELConfigures PDN pin as PDN or SYNCN
R0[5]SYNCGenerates SYNC signal through serial interface
R57[9], R63[9], R68[9], R73[9]CH1_GLITCHLESS_EN, CH2_GLITCHLESS_EN, CH3_GLITCHLESS_EN, CH4_GLITCHLESS_ENEnables Glitchless switching for OUT1/OUT2/OUT3/OUT4
R57[3], R63[3], R68[3], R73[3]CH1_SYNC_EN, CH2_SYNC_EN, CH3_SYNC_EN, CH4_SYNC_ENEnables SYNC for OUT1/OUT2/OUT3/OUT4
R57[1], R63[1], R68[1], R73[1]CH1_MUTESEL, CH2_MUTESEL, CH3_MUTESEL, CH4_MUTESELSets Output level when mute on OUT1/OUT2/OUT3/OUT4
R57[0], R63[0], R68[0], R73[0]CH1_MUTE, CH2_MUTE, CH3_MUTE, CH4_MUTEMutes output on OUT1/OUT2/OUT3/OUT4