SLASF61A January   2023  – September 2023 DAC539G2-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: Voltage Output
    6. 6.6  Electrical Characteristics: Comparator Mode
    7. 6.7  Electrical Characteristics: General
    8. 6.8  Timing Requirements: I2C Standard Mode
    9. 6.9  Timing Requirements: I2C Fast Mode
    10. 6.10 Timing Requirements: I2C Fast Mode Plus
    11. 6.11 Timing Requirements: SPI Write Operation
    12. 6.12 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 0)
    13. 6.13 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 1)
    14. 6.14 Timing Requirements: GPIO
    15. 6.15 Timing Diagrams
    16. 6.16 Typical Characteristics: Voltage Output
    17. 6.17 Typical Characteristics: Comparator
    18. 6.18 Typical Characteristics: General
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Smart Digital-to-Analog Converter (DAC) Architecture
      2. 7.3.2 Programming Interface
      3. 7.3.3 Nonvolatile Memory (NVM)
    4. 7.4 Device Functional Modes
      1. 7.4.1 GPI-to-Voltage Converter
        1. 7.4.1.1 Voltage Reference and DAC Transfer Function
        2. 7.4.1.2 Power-Supply as Reference
        3. 7.4.1.3 Internal Reference
        4. 7.4.1.4 External Reference
      2. 7.4.2 Voltage-to-PWM Converter
        1. 7.4.2.1 Function Generation
          1. 7.4.2.1.1 Triangular Waveform Generation
          2. 7.4.2.1.2 Sawtooth Waveform Generation
          3. 7.4.2.1.3 PWM Frequency Correction
      3. 7.4.3 Device Reset and Fault Management
        1. 7.4.3.1 Power-On Reset (POR)
        2. 7.4.3.2 External Reset
        3. 7.4.3.3 Register-Map Lock
        4. 7.4.3.4 NVM Cyclic Redundancy Check (CRC)
          1. 7.4.3.4.1 NVM-CRC-FAIL-USER Bit
          2. 7.4.3.4.2 NVM-CRC-FAIL-INT Bit
      4. 7.4.4 Power-Down Mode
    5. 7.5 Programming
      1. 7.5.1 SPI Programming Mode
      2. 7.5.2 I2C Programming Mode
        1. 7.5.2.1 F/S Mode Protocol
        2. 7.5.2.2 I2C Update Sequence
          1. 7.5.2.2.1 Address Byte
          2. 7.5.2.2.2 Command Byte
        3. 7.5.2.3 I2C Read Sequence
    6. 7.6 Register Maps
      1. 7.6.1  NOP Register (address = 00h) [reset = 0000h]
      2. 7.6.2  DAC-X-VOUT-CMP-CONFIG Register (address = 15h, 03h) [reset = 0400h]
      3. 7.6.3  COMMON-CONFIG Register (address = 1Fh) [reset = 03F9h]
      4. 7.6.4  COMMON-TRIGGER Register (address = 20h) [reset = 0000h]
      5. 7.6.5  FUNCTION-TRIGGER Register (address = 21h) [reset = 0001h]
      6. 7.6.6  GENERAL-STATUS Register (address = 22h) [reset = 2068h]
      7. 7.6.7  DEVICE-MODE-CONFIG Register (address = 25h) [reset = 8040h]
      8. 7.6.8  INTERFACE-CONFIG Register (address = 26h) [reset = 0000h]
      9. 7.6.9  STATE-MACHINE-CONFIG Register (address = 27h) [reset = 0003h]
      10. 7.6.10 SRAM-CONFIG Register (address = 2Bh) [reset = 0000h]
      11. 7.6.11 SRAM-DATA Register (address = 2Ch) [reset = 0000h]
      12. 7.6.12 FUNCTION-CONFIG Register (SRAM address = 20h) [reset = 007Ah]
      13. 7.6.13 FUNCTION-MAX Register (SRAM address = 21h) [reset = B900h]
      14. 7.6.14 FUNCTION-MIN Register (SRAM address = 22h) [reset = 1900h]
      15. 7.6.15 GPI-DEBOUNCE Register (SRAM address = 23h) [reset = 0138h]
      16. 7.6.16 VOUT-DATA-X Register (SRAM address = 24h to 2Bh) [reset = see #GUID-D64978E3-E8F0-4408-A2C1-8C72D24777EC/X6961 ]
      17. 7.6.17 PWM-FREQUENCY-ERROR Register (SRAM address = 9Eh) [reset = device-specific]
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2.2 Detailed Design Procedure

Calculate the PWM frequency by using the time steps and code step from Table 7-27, either Equation 4 for a triangle wave or Equation 5 for a sawtooth wave, and the selected FUNCTION-MAX and FUNCTION-MIN DAC codes. Section 7.4.2.1 describes the details on the function generation settings. The FUNCTION-MAX and FUNCTION-MIN DAC codes represent the peaks of the triangle or sawtooth waveforms. To achieve a frequency of 100 Hz, this example uses a triangle wave with a margin high of 725, a margin low of 100, slew rate of 8 μs, and code step of 1 LSB:

Equation 7. fTRIANGLE=12×8 μs×CEILING(725-1001)=100 Hz

The DAC539G2-Q1 is a 10-bit device, which means the maximum DAC code is 1023d. Choose margin-high and -low values that are away from the endpoints to avoid effects from the zero-code and full-scale errors.

For small step sizes, the duty cycles can be estimated by:

Equation 8. Duty_CycleTRIANGLE=FUNCTION_MAX-VOUT_DATA_XCEILING(FUNCTION_MAX-FUNCTION_MINCODE_STEP)=100 Hz

Where VOUT_DATA_X is the DAC code set in the LUT for every combination of the GPI inputs (VOUT-DATA-X).

For a duty cycle duty cycle of 12.5%, the VOUT_DATA_X is calculated by:

Equation 9. VOUT_DATA_XTRIANGLE=FUNCTION_MAX-CEILING(FUNCTION_MAX-FUNCTION_MAXCODE_STEP)×Duty_Cycle=725-2×CEILING(725-1001)×0.125=646.88

This result is rounded up to 647d (0x287). Table 8-2 lists the LUT table values for the remaining duty cycles.

Table 8-2 LUT Codes
DUTY CYCLE VOUT_DATA_X
12.5% 0x287
25% 0x239
37.5% 0x1EB
50% 0x19D
62.5% 0x14E
75% 0x100
87.5% 0x0B2
100% 0x064

The LUT codes are written to the DAC outputs depending on the state of the three GPI pins. The DAC codes do not have to increase chronologically with the GPIs. A programmable delay can be used so that the DAC output changes only after the GPIs have settled to avoid any switching noise on the output. The delay setting is 16 bits with a step size of 160 μs, and is stored in the GPI-DEBOUNCE SRAM register. Set the delay code to 312d for a 50-ms delay.

The oscillator error is directly reflected on the output frequency of the PWM signal. This error can be compensated for by adjusting the margin-high and -low codes to adjust the frequency of the triangle wave generated on channel 0. The DAC539G2-Q1 oscillator error is stored in SRAM register 0x9E. This error is a 6-bit value with a code step of 0.2%, so the margin-high and -low codes can be modified to correct for –6.4% to +6.2% of error. For example, for code 0x2C, the oscillator error is –4%, or the frequency is 4% higher than the target. Increase the margin high – margin low differential value so that the calculated frequency is 4% lower than the target value.

Follow these guidelines to set up the registers on the DAC539G2-Q1:

  • Stop the state machine before updating the application parameters by writing 0 to the STATE-MACHINE-CONFIG register.
  • Set all of the application parameters shown in Table 8-3. These locations must be used to save the settings in the NVM. For example, the DAC register locations for FUNCTION-CONFIG, FUNCTION-MAX, and FUNCTION-MIN are not mapped to the NVM and are not saved when an NVM write is triggered.
  • If the function generator is already running, the function generator must be stopped before any changes to the triangle wave take effect. Write a 0 to the START-FUNC field in the COMMON-DAC-TRIG register (0x21) to stop the function generator. The function generator is automatically started when the state machine is enabled.
  • VOUT-DATA-0 and VOUT-DATA-7 correspond to the three GPIs being set to 0b000 and 0b111, respectively.
  • Configure the reference for both channels in the DAC-X-VOUT-CMP-CONFIG register. Set the reference for channel 1 to the same reference chosen for channel 0.
  • Configure DAC channel 0 in triangle-wave mode with the chosen slew rate and code step in the FUNCTION-CONFIG SRAM register.
  • Set the margin-high and margin-low codes for the channel 0 triangle wave in the FUNCTION-MAX and FUNCTION-MIN SRAM registers, respectively.
  • Power on the DAC outputs in voltage mode using the COMMON-CONFIG register.
  • Set the DEVICE-MODE-CONFIG register to 0x8040.
  • Start the state machine by writing 3d to the STATE-MACHINE-CONFIG.
  • Trigger an NVM write by setting the NVM-PROG bit in the COMMON-TRIGGER register (0x20) to 1.
Table 8-3 Application Parameters
REGISTER FIELD NAME ADDRESS [FIELD] ADDRESS LOCATION
FUNCTION-CONFIG 0x20[10:9][6:0] SRAM
FUNCTION-MAX 0x21[15:6] SRAM
FUNCTION-MIN 0x22[15:6] SRAM
GPI-DEBOUNCE 0x23[15:0] SRAM
VOUT-DATA-0 0x24[15:6] SRAM
VOUT-DATA-1 0x25[15:6] SRAM
VOUT-DATA-2 0x26[15:6] SRAM
VOUT-DATA-3 0x27[15:6] SRAM
VOUT-DATA-4 0x28[15:6] SRAM
VOUT-DATA-5 0x29[15:6] SRAM
VOUT-DATA-6 0x2A[15:6] SRAM
VOUT-DATA-7 0x2B[15:6] SRAM
DAC-0-VOUT-CMP-CONFIG 0x15[12:10][4:0] Register
DAC-1-VOUT-CMP-CONFIG 0x03[12:10][4:0] Register
COMMON-CONFIG 0x1F[15:0] Register
DEVICE-MODE-CONFIG 0x25[15:0] Register
STATE-MACHINE-CONFIG 0x27[2:0] Register
Only the bits listed in the address column of Table 8-3 are saved in NVM and used in the state machine. For example, only bits 12 to 10, and 4 to 0 are saved in NVM for the DAC-X-VOUT-CMP-CONFIG registers.

The pseudocode for this application example is as follows: 

//SYNTAX: WRITE <REGISTER NAME(Hex Code)>, <MSB DATA>, <LSB DATA>
//Stop the state machine
WRITE STATE-MACHINE-CONFIG(0x27), 0x00, 0x03
//Stop the function generator
WRITE COMMON-DAC-TRIG(0x21), 0x00, 0x00
//Set the code step, slew rate, and waveform mode 
WRITE FUNCTION-CONFIG(SRAM 0x20), 0x00, 0x02
WRITE FUNCTION-MAX(SRAM 0x21), 0xB5, 0x40
WRITE FUNCTION-MIN(SRAM 0x22), 0x19, 0x00
//Set the programmable debounce delay (this is the device default) 
WRITE GPI-DEBOUNCE(SRAM 0x23), 0x01, 0x38
//Set the LUT values
WRITE VOUT-DATA-0(SRAM 0x24), 0xA1, 0xC0
WRITE VOUT-DATA-1(SRAM 0x25), 0x8E, 0x40
WRITE VOUT-DATA-2(SRAM 0x26), 0x7A, 0xC0
WRITE VOUT-DATA-3(SRAM 0x27), 0x67, 0x40
WRITE VOUT-DATA-4(SRAM 0x28), 0x53, 0x80
WRITE VOUT-DATA-5(SRAM 0x29), 0x40, 0x00
WRITE VOUT-DATA-6(SRAM 0x2A), 0x2C, 0x80
WRITE VOUT-DATA-7(SRAM 0x2B), 0x18, 0xC0
//Set the channel 0 reference to VDD (this is the device default) 
WRITE DAC-0-VOUT-CMP-CONFIG(0x15), 0x04, 0x00
//Set channel 1 reference to VDD (this is the device default) 
WRITE DAC-1-VOUT-CMP-CONFIG(0x03), 0x04, 0x00
//Power on the DAC channels (this is the device default) 
WRITE COMMON-CONFIG(0x1F), 0x03, 0xF9
//Set the device mode (this is the device default) 
WRITE DEVICE-MODE-CONFIG(0x25), 0x80, 0x40
//Start the state machine
WRITE STATE-MACHINE-CONFIG(0x27), 0x00, 0x03
//Save settings to NVM
WRITE COMMON-TRIGGER(0x20), 0x00, 0x02