SLASF61A January   2023  – September 2023 DAC539G2-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: Voltage Output
    6. 6.6  Electrical Characteristics: Comparator Mode
    7. 6.7  Electrical Characteristics: General
    8. 6.8  Timing Requirements: I2C Standard Mode
    9. 6.9  Timing Requirements: I2C Fast Mode
    10. 6.10 Timing Requirements: I2C Fast Mode Plus
    11. 6.11 Timing Requirements: SPI Write Operation
    12. 6.12 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 0)
    13. 6.13 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 1)
    14. 6.14 Timing Requirements: GPIO
    15. 6.15 Timing Diagrams
    16. 6.16 Typical Characteristics: Voltage Output
    17. 6.17 Typical Characteristics: Comparator
    18. 6.18 Typical Characteristics: General
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Smart Digital-to-Analog Converter (DAC) Architecture
      2. 7.3.2 Programming Interface
      3. 7.3.3 Nonvolatile Memory (NVM)
    4. 7.4 Device Functional Modes
      1. 7.4.1 GPI-to-Voltage Converter
        1. 7.4.1.1 Voltage Reference and DAC Transfer Function
        2. 7.4.1.2 Power-Supply as Reference
        3. 7.4.1.3 Internal Reference
        4. 7.4.1.4 External Reference
      2. 7.4.2 Voltage-to-PWM Converter
        1. 7.4.2.1 Function Generation
          1. 7.4.2.1.1 Triangular Waveform Generation
          2. 7.4.2.1.2 Sawtooth Waveform Generation
          3. 7.4.2.1.3 PWM Frequency Correction
      3. 7.4.3 Device Reset and Fault Management
        1. 7.4.3.1 Power-On Reset (POR)
        2. 7.4.3.2 External Reset
        3. 7.4.3.3 Register-Map Lock
        4. 7.4.3.4 NVM Cyclic Redundancy Check (CRC)
          1. 7.4.3.4.1 NVM-CRC-FAIL-USER Bit
          2. 7.4.3.4.2 NVM-CRC-FAIL-INT Bit
      4. 7.4.4 Power-Down Mode
    5. 7.5 Programming
      1. 7.5.1 SPI Programming Mode
      2. 7.5.2 I2C Programming Mode
        1. 7.5.2.1 F/S Mode Protocol
        2. 7.5.2.2 I2C Update Sequence
          1. 7.5.2.2.1 Address Byte
          2. 7.5.2.2.2 Command Byte
        3. 7.5.2.3 I2C Read Sequence
    6. 7.6 Register Maps
      1. 7.6.1  NOP Register (address = 00h) [reset = 0000h]
      2. 7.6.2  DAC-X-VOUT-CMP-CONFIG Register (address = 15h, 03h) [reset = 0400h]
      3. 7.6.3  COMMON-CONFIG Register (address = 1Fh) [reset = 03F9h]
      4. 7.6.4  COMMON-TRIGGER Register (address = 20h) [reset = 0000h]
      5. 7.6.5  FUNCTION-TRIGGER Register (address = 21h) [reset = 0001h]
      6. 7.6.6  GENERAL-STATUS Register (address = 22h) [reset = 2068h]
      7. 7.6.7  DEVICE-MODE-CONFIG Register (address = 25h) [reset = 8040h]
      8. 7.6.8  INTERFACE-CONFIG Register (address = 26h) [reset = 0000h]
      9. 7.6.9  STATE-MACHINE-CONFIG Register (address = 27h) [reset = 0003h]
      10. 7.6.10 SRAM-CONFIG Register (address = 2Bh) [reset = 0000h]
      11. 7.6.11 SRAM-DATA Register (address = 2Ch) [reset = 0000h]
      12. 7.6.12 FUNCTION-CONFIG Register (SRAM address = 20h) [reset = 007Ah]
      13. 7.6.13 FUNCTION-MAX Register (SRAM address = 21h) [reset = B900h]
      14. 7.6.14 FUNCTION-MIN Register (SRAM address = 22h) [reset = 1900h]
      15. 7.6.15 GPI-DEBOUNCE Register (SRAM address = 23h) [reset = 0138h]
      16. 7.6.16 VOUT-DATA-X Register (SRAM address = 24h to 2Bh) [reset = see #GUID-D64978E3-E8F0-4408-A2C1-8C72D24777EC/X6961 ]
      17. 7.6.17 PWM-FREQUENCY-ERROR Register (SRAM address = 9Eh) [reset = device-specific]
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics: Voltage Output

minimum and maximum specifications at TA = –40°C to +125°C and typical specifications at TA = 25°C, 1.7 V ≤ VDD ≤ 5.5 V, DAC reference tied to VDD, gain = 1 ×, DAC output pin (OUT) loaded with resistive load (RL = 5 kΩ to AGND) and capacitive load (CL = 200 pF to AGND), and digital inputs at VDD or AGND (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
STATIC PERFORMANCE
Resolution 10 Bits
INL Integral nonlinearity(1) –1.25 1.25 LSB
DNL Differential nonlinearity(1) –1 1 LSB
Zero-code error(4) Code 0d into DAC, external reference, VDD = 5.5 V 6 12 mV
Zero-code error(4) Code 0d into DAC, internal VREF, gain = 4 ×,
VDD = 5.5 V		 6 15 mV
Zero-code error temperature coefficient(4) ±10 µV/°C
Offset error(4) 1.7 V ≤ VDD < 2.7 V, VFB pin shorted to VOUT, DAC code: 8d –0.75 0.3 0.75 %FSR
2.7 V ≤ VDD ≤ 5.5 V, VFB pin shorted to VOUT, DAC code: 8d –0.5 0.25 0.5
Offset-error temperature coefficient(4) VFB pin shorted to VOUT, DAC code: 8d ±0.0003 %FSR/°C
Gain error(4) Between end-point codes: 8d and 1016d –0.5 0.25 0.5 %FSR
Gain-error temperature coefficient(4) Between end-point codes: 8d and 1016d ±0.0008 %FSR/°C
Full-scale error(4) 1.7 V ≤ VDD < 2.7 V, DAC at full-scale –1 1 %FSR
Full-scale error(4) 2.7 V ≤ VDD ≤ 5.5 V, DAC at full-scale –0.6 0.6 %FSR
Full-scale-error temperature coefficient(4) DAC at full-scale ±0.0008 %FSR/°C
OUTPUT
Output voltage Reference tied to VDD 0 VDD V
CL Capacitive load(2) RL = infinite, phase margin = 30° 200 pF
Phase margin = 30° 1000
Load regulation DAC at midscale, –10 mA ≤ IOUT ≤ 10 mA,
VDD = 5.5 V, VREF = 5.5 V, VREF not shorted to VDD		 0.007 mV/mA
Short-circuit current VDD = 1.7 V, full-scale output shorted to AGND or
zero-scale output shorted to VDD		 15 mA
VDD = 2.7 V, full-scale output shorted to AGND or
zero-scale output shorted to VDD		 50
VDD = 5.5 V, full-scale output shorted to AGND or
zero-scale output shorted to VDD		 60
Output-voltage headroom(2) To VDD (DAC output unloaded, internal reference = 1.21 V), VDD ≥ 1.21 V × gain + 0.2 V 0.2 V
To VDD and to AGND
(DAC output unloaded, external reference at VDD (gain = 1 ×), the VREF pin is not shorted to VDD)		 0.8 %FSR
To VDD and to AGND (ILOAD = 10 mA at VDD = 5.5 V, ILOAD = 3 mA at VDD = 2.7 V, ILOAD = 1 mA at VDD =
1.8 V), external reference at VDD (gain = 1 ×), the VREF pin is not shorted to VDD)		 10 %FSR
VOUT dc output impedance DAC output enabled and DAC code = midscale, 
VDD = 5.5 V, external reference mode		 0.007 Ω
DAC output enabled and DAC code = 8d, 
VDD = 5.5 V, external reference mode		 0.25
DAC output enabled and DAC code = 1016d, 
VDD = 5.5 V, external reference mode		 0.25
ZO VFB dc output impedance(3) DAC output enabled, internal reference
(gain = 1.5 × or 2 ×)		 400 500 600 kΩ
DAC output enabled, internal reference
(gain = 3 × or 4 ×)		 325 400 485
Power supply rejection ratio (dc) Internal VREF, gain = 2 ×, DAC at midscale,
VDD = 5 V ±10%		 0.25 mV/V
DYNAMIC PERFORMANCE
tsett Output voltage settling time 1/4 to 3/4 scale and 3/4 to 1/4 scale settling to 10%FSR, VDD = 5.5 V 20 µs
1/4 to 3/4 scale and 3/4 to 1/4 scale settling to 10%FSR, VDD = 5.5 V, internal VREF, gain = 4 × 25
Slew rate VDD = 5.5 V 0.3 V/µs
Power-on glitch magnitude At start-up (DAC output disabled) 75 mV
At start-up (DAC output disabled), RL = 100 kΩ 200
Output-enable glitch magnitude DAC output disabled to enabled (DAC registers at zero scale), RL = 100 kΩ 250 mV
Vn Output noise voltage (peak to peak) f = 0.1 Hz to 10 Hz, DAC at midscale, VDD = 5.5 V 50 µVPP
Internal VREF, gain = 4 ×, f = 0.1 Hz to 10 Hz,
DAC at midscale, VDD = 5.5 V		 90
Output noise density f = 1 kHz, DAC at midscale, VDD = 5.5 V 0.35 µV/√Hz
Internal VREF, gain = 4 ×, f = 1 kHz, DAC at midscale, VDD = 5.5 V 0.9
Power supply rejection ratio (ac)(3) Internal VREF, gain = 4 ×, 200-mV 50-Hz or 60-Hz sine wave superimposed on power supply voltage, DAC at midscale −68 dB
Code change glitch impulse ±1 LSB change around midscale (including feedthrough) 10 nV-s
Code change glitch impulse magnitude ±1 LSB change around midscale (including feedthrough) 15 mV
POWER
IDD Current flowing into VDD(4) (5) Normal operation, DACs at full scale, digital pins static, external reference at VDD but the VREF pin is not shorted to VDD 150 µA/ch
(1) Measured with DAC output unloaded. For external reference and internal reference VDD ≥ 1.21 × gain + 0.2 V, between end-point codes: 8d and 1016d.
(2) Specified by design and characterization, not production tested.
(3) Specified with 200-mV headroom with respect to reference value when internal reference is used.
(4) Measured with DAC output unloaded.
(5) The total power consumption is calculated by IDD × (total number of channels powered on) + (sleep-mode current).