The DACx300x are
single-channel and dual-channel buffered, force-sense output, voltage-output and
current-output smart DACs that include an NVM and internal reference, and available
in a tiny 3-mm × 3-mm package.
- In voltage-output mode, short the OUTx and FBx pins for each channel. In
current-output mode, leave the FBx pins unconnected. The FBx pins function as
inputs in comparator mode.
- The external reference must not exceed VDD, either during transient or
steady-state conditions. For the best Hi-Z output performance, use a pullup
resistor on the VREF pin to VDD.
- In case VDD remains floating during the off condition, place a 100-kΩ resistor
to AGND for proper detection of the VDD off condition for voltage
- All the digital outputs are open drain; use external pullup resistors on these
- The interface protocol is detected at power-on, and the device locks to the
protocol as long as VDD is on.
- When allocating nonoverlapping
I2C addresses on a system I2C bus, consider the
broadcast address as well. I2C timeout can be enabled for
- SPI mode is 3-wire by default. Configure the GPIO pin as SDO in the NVM for SPI
readback capability. The SPI clock speed in readback mode is slower than in
- Power-down mode sets the DAC
outputs to Hi-Z by default. Change the configuration appropriately for different
power-down settings. The DAC channels can also power-up with a programmed DAC
code in NVM.