SLASF48 May   2022

PRODUCTION DATA

1. Features
2. Applications
3. Description
4. Revision History
5. Pin Configuration and Functions
6. Specifications
7. Detailed Description
1. 7.1 Overview
2. 7.2 Functional Block Diagram
3. 7.3 Feature Description
4. 7.4 Device Functional Modes
1. 7.4.1 Voltage-Output Mode
1. 7.4.1.1 Voltage Reference and DAC Transfer Function
2. 7.4.2 Current-Output Mode
3. 7.4.3 Comparator Mode
4. 7.4.4 Fault-Dump Mode
5. 7.4.5 Application-Specific Modes
1. 7.4.5.1 Voltage Margining and Scaling
2. 7.4.5.2 Function Generation
6. 7.4.6 Device Reset and Fault Management
7. 7.4.7 Power-Down Mode
5. 7.5 Programming
1. 7.5.1 SPI Programming Mode
2. 7.5.2 I2C Programming Mode
1. 7.5.2.1 F/S Mode Protocol
2. 7.5.2.2 I2C Update Sequence
3. 7.5.2.3 I2C Read Sequence
3. 7.5.3 General-Purpose Input/Output (GPIO) Modes
6. 7.6 Register Map
8. Application and Implementation
1. 8.1 Application Information
2. 8.2 Typical Application
9. Power Supply Recommendations
10. 10Layout
11. 11Device and Documentation Support
12. 12Mechanical, Packaging, and Orderable Information

• RTE|16
• RTE|16

### 7.3.4 Power Consumption

The power consumption of the DACx300x in sleep mode and deep-sleep mode are provided in Section 6.20. In normal operation, the total power consumption of the device depends on the number of channels powered on and the output mode of each channel (voltage or current). In current-output mode, the IDD also depends on the output range. The IDD calculation excludes the load current. For example, in the ±250 μA output mode with a DAC setting of +125 μA, the total current drawn through the VDD pin is the total IDD plus 125 μA. The total IDD in normal operation can be calculated using Equation 1.

Equation 1. ${\mathrm{P}}_{\mathrm{N}\mathrm{O}\mathrm{R}\mathrm{M}\mathrm{A}\mathrm{L}_\mathrm{M}\mathrm{O}\mathrm{D}\mathrm{E}}={\mathrm{V}}_{\mathrm{D}\mathrm{D}}×\left({\mathrm{I}}_{\mathrm{D}\mathrm{D}_\mathrm{S}\mathrm{L}\mathrm{E}\mathrm{E}\mathrm{P}}+{\mathrm{I}}_{\mathrm{D}\mathrm{D}_\mathrm{R}\mathrm{E}\mathrm{F}}\right)+\sum _{\mathrm{X}=0}^{3}\left({\mathrm{V}}_{\mathrm{D}\mathrm{D}}×{\mathrm{I}}_{\mathrm{D}\mathrm{D}_\mathrm{X}}\right)$

where:

• IDD_SLEEP is the current through VDD in sleep mode when all the channels and internal reference are powered down.
• IDD_REF is the reference current, which is:
• either the current drawn by the reference input impedance when VDD is used as reference
• or the current drawn by the internal reference, if enabled
• IDD_X is the current through VDD for every powered-on channel-X.
Note: When an external reference is used, the current is calculated mainly as the current sourced from the external reference, which is equal to the reference voltage divided by the input impedance of the VREF pin.