The DACx300x provides a feature to save
a few registers into the NVM when the FAULT-DUMP bit is triggered or
when the GPIO mapped to fault-dump is triggered (see also Table 7-18). This feature is useful in system-level fault management to
capture the state of the device or system just before a fault is
triggered, and to allow diagnosis after the fault has occurred. The
registers saved when fault-dump is triggered, are:
Note: When the
fault-dump cycle is in progress, any change in the data can
corrupt the final outcome. Make sure the comparator and the
DAC codes are stable during the NVM write cycle.Table 7-3
shows the storage format of the registers in the NVM.
Table 7-3 Fault-Dump NVM
The data captured in the
NVM after the fault dump can be read in a specific sequence:
- Set the
EE-READ-ADDR bit to 0b in the COMMON-CONFIG
register, to select row1 of the NVM.
the read of the selected NVM row by writing 1 to the
READ-ONE-TRIG in the COMMON-TRIGGER register; this
bit autoresets. This action copies that data from
the selected NVM row to SRAM addresses 0x9D (LSB 16
bits from the NVM) and 0x9E (MSB 16 bits from the
- To read
the SRAM data:
- Write 0x009D to the SRAM-CONFIG register.
- Read the data from the SRAM-DATA register to get
the LSB 16 bits.
- Write 0x009E to the SRAM-CONFIG register.
- Read the data from the SRAM-DATA register again
to get the MSB bits.
- Set the
EE-READ-ADDR bit to 1b in the COMMON-CONFIG
register, to select row2 of the NVM. Repeat steps 2