For power FETs a typically specified parameter is the total gate charge required to turn-on or turn-off the FET. The selection of the illumination buck-converter FETs with respect to their total gate charge is mainly relative to gate-source rise and fall times. For proper operation it is advised to have the gate-source rise and fall times maximum on the order of 20 ns–30 ns. Given the typical high-side driver pullup resistance of about 5 Ohm, an equivalent maximum gate capacitance of 4-6nF is appropriate. Since the gate-source swing is about 5 V, a total turn-on/off gate charge of maximum 20 nC–30 nC is therefore advised.

The DPLA3005 has built-in non-overlap timing to prevent that both the high-side and low-side FET of the illumination buck converter are turned-on simultaneously. The typical non-overlap timing is about 35 ns. In most applications this should give sufficient margins. On top of this non-overlap timing the DLPA3005 measures the gate-source voltage of the external FETs to determine whether a FET is actually on or off. This measurement is done at the pins of the DLPA3005. For the low-side FET this measurement is done between ILLUM_LSIDE_DRIVE and ILLUM_A_GND. Similarly, for the high-side FET the gate-source voltage is measured between ILLUM_HSIDE_DRIVE and ILLUM_A_SW. The location of these measurement nodes imply that at all times no additional drivers or circuitry should be inserted between the DLPA3005 and the external power FETs of the buck converter. Inserting circuitry (delays) could potentially lead to incorrect on-off detection of the FETs and cause shoot-through currents. These shoot-through currents are negatively affecting the efficiency, but more seriously can potentially damage the power FETs.

For the LED selection switches no specific selection criteria are present on gate charge / timing. This is because the timing of the LED selection signals is in the microsecond range rather than nanosecond range.