DLPS167 March 2024 DLPC964
PRODUCTION DATA
The FPGA_INTERRUPT_ENABLE_CONTROL register contains the Enables for the Watchdog timeout status and the four HSS Channels Hard Error status.
Bit(s) | Description | Reset | Type | Notes |
---|---|---|---|---|
0 | Fieldname: Reserved | 0x0 | ||
1 | SPARE | 0x0 | ||
2 | Fieldname: ERROR_RSC_WATCHDOG_INT_EN_FLD | 0x0 | W | |
'1': allow Watchdog timeout to assert Controller interrupt output. | ||||
If this bit and FPGA_INTERRUPT_STATUS register bit 2 are set, the Controller interrupt output would be asserted | ||||
3 | Fieldname: HSS_CH0_HARD_ERROR_INT_EN_FLD | 0x0 | W | |
'1': allow Input Aurora Channel 0 hard error to assert Controller interrupt output. | ||||
If this bit and FPGA_INTERRUPT_STATUS register bit 3 are set, the Controller interrupt output would be asserted | ||||
4 | Fieldname: HSS_CH1_HARD_ERROR_INT_EN_FLD | 0x0 | W | |
'1': allow Input Aurora Channel 1 hard error to assert Controller interrupt output. | ||||
If this bit and FPGA_INTERRUPT_STATUS register bit 4 are set, the Controller interrupt output would be asserted | ||||
5 | Fieldname: HSS_CH2_HARD_ERROR_INT_EN_FLD | 0x0 | W | |
'1': allow Input Aurora Channel 2 hard error to assert Controller interrupt output. | ||||
If this bit and FPGA_INTERRUPT_STATUS register bit 5 are set, the Controller interrupt output would be asserted | ||||
6 | Fieldname: HSS_CH3_HARD_ERROR_INT_EN_FLD | 0x0 | W | |
'1': allow Input Aurora Channel 3 hard error to assert Controller interrupt output. | ||||
If this bit and FPGA_INTERRUPT_STATUS register bit 6 are set, the Controller interrupt output would be asserted | ||||
7 | SPARE | 0x0 | ||
31:8 | UNUSED | 0x0 |