SPRS976E November 2016 – May 2018 DM505
PRODUCTION DATA.
Figure 7-25 shows the placement rules for the device as well as the LPDDR2 memory device. Placement restrictions are provided as a guidance to restrict maximum trace lengths and allow for proper routing space.
NO. | PARAMETER | MIN | MAX | UNIT |
---|---|---|---|---|
1 | X1 Offset(2)(3) | 900 | mils | |
2 | Y Offset | 200 | mils | |
3 | Clearance from non-LPDDR2 signal to LPDDR2 keepout region(4)(5) | 4 | w |