2 Revision History
Changes from July 31, 2017 to May 5, 2018 (from D Revision (July 2017) to E Revision)
- Updated “ARM“ references to “Arm” in Section 1.1, FeaturesGo
- Updated “ARM“ references to “Arm” in Table 3-1, Device ComparisonGo
- Added clarification notes to Section 4.2, Pin AttributesGo
- Updated I/O VOLTAGE VALUE column in Table 4-1, Pin Attributes to include 1.2V to all ddr signalsGo
- Removed MUX16 option in Table 4-1, Pin AttributesGo
- Updated some GPMC ball reset release muxmode values in Table 4-1, Pin AttributesGo
- Removed balls from Table 4-16, McASP Signal DescriptionsGo
- Updated “ARM“ references to “Arm” in Table 4-26, INTC Signal DescriptionsGo
- Added missing balls in Table 4-29, Unused Balls Specific Connection RequirementsGo
- Added recommended and absolute maximum voltage values for vdds_ddr* power pins when LPDDR2 and DDR2 are usedGo
- Updated Table 5-5, Maximum Supported FrequencyGo
- Removed voltage high level limits from Table 5-11, LVCMOS CSI2 DC Electrical CharacteristicsGo
- Added references to notes under Table 5-11, LVCMOS CSI2 DC Electrical CharacteristicsGo
- Updated Section 5.9.1, Timing Parameters and InformationGo
- Updated power down sequencingGo
- Updated Output Clocks sectionGo
- Updated DPLL CLKOUT output frequency in Table 5-26, DPLL CharacteristicsGo
- Updated McSPI and QSPI timing figuresGo
- Updated Phase polarity in all QSPI timing figuresGo
- Added qspi1_cs1 to all QSPI IOSETs in Table 5-51, QSPI IOSETsGo
- Added Table 5-59, McASP2 IOSETsGo
- Added CAN delay time receive and transmit parameters in relation to the shift registersGo
- Updated "ARM" references to "Arm" Table 5-82, Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG With RTCKGo
- Updated “ARM“ references to “Arm” in Section 6, Detailed DescriptionGo
- Added Section 7.3.7, Loss of Input Power Event Go
- Added new parameter in Table 7-11, Length Mismatch Guidelines for CSI-2 (1.5 Gbps) Go
- Updated “ARM“ references to “Arm” in the Trademarks ListGo