SNLS647 Data sheet

SNLS647I December 2019 – August 2025 DP83826E , DP83826I

PRODUCTION DATA

Package Options

Mechanical Data (Package|Pins)

RHB|32
- MPQF130D

Thermal pad, mechanical data (Package|Pins)

RHB|32
- QFND257K

Orderable Information

7.6 Timing Requirements

⁽¹⁾

PARAMETER		MIN	NOM	MAX	UNIT
Power Up Timing
T1	Voltage ramp duration ( 0% to 100% VDDIO)	0.5		50	ms
T2	Supply sequencing VDDA3V3 followed by VDDIO or VDDIO followed by VDDA3V3 ⁽²⁾ ⁽⁴⁾	0		200	ms
T3	Voltage ramp duration ( 0% to 100% of VDDA3V3)	0.5		50	ms
T4	POR release time / Powerup to SMI ready: Post power-up stabilization time prior to MDC preamble for register access			50	ms
T5	Powerup to FLP		1500		ms
	Pedestal voltage on VDDA3V3, VDDIO before Power Ramp			0.3	V
Reset Timing
T1	RESET PULSE Width: Miminum reset pulse width to be able to reset (w/o debouncing caps)	25			µs
T2	Reset to SMI ready: Post reset stabilization time prior to MDC preamble for register access			2	ms
T3	Reset to FLP		1500		ms
	Reset to 100M signaling (strapped mode)		0.5		ms
	Reset to RMII leader clock		0.2		ms
Fast Link Pulse Timing
T1	Clock pulse to clock pulse period	111	125	139	μs
T2	Clock pulse to data pulse period	55.5	62.5	69.5	μs
T3	Clock/Data pulse width		104		ns
T4	FLP burst to FLP burst period	8	16	24	ms
T5	FLP burst width		2		ms
	Pulse in burst width	17		33
Link Up Timing
	Fast Link Drop enabled using straps , 150 meter cable			10	µs
	Fast Link Drop Time using Mode 1 (Signal/Energy Loss indication)			10	µs
	Fast Link Drop Time using Mode 2 (Low SNR Threshold) ⁽⁵⁾			10	µs
	Fast Link Drop Time using Mode 3 (MLT3 Error count) ⁽⁵⁾			10	µs
	Fast Link Drop Time using Mode 4 (RX Error count)			10	µs
	Fast Link Drop Time using Mode 5 (Descrambler link drop) ⁽⁵⁾			11	µs
100M EEE timings
	Sleep time		210		µs
	Quiet time		20		ms
	Wake Time (Tw_sys_tx)		36		µs
	Refresh time		200		µs
100M MII Receive Timing
T1	RX_CLK high / low time	16	20	24	ns
T2	RX_D[3:0], RX_ER, RX_DV delay from RX_CLK rising	20		28	ns
100M MII Transmit Timing
T1	TX_CLK high / low time	16	20	24	ns
T2	TX_D[3:0], TX_ER, TX_EN setup to TX_CLK	10			ns
T3	TX_D[3:0], TX_ER, TX_EN hold from TX_CLK	0			ns
10M MII Receive Timing
T1	RX_CLK high / low time⁽³⁾	160	200	240	ns
T2	RX_D[3:0], RX_ER, RX_DV delay from RX_CLK rising⁽³⁾	100		300	ns
10M MII Transmit Timing
T1	TX_CLK high / low time	190	200	210	ns
T2	TX_D[3:0], TX_ER, TX_EN setup to TX_CLK	25			ns
T3	TX_D[3:0], TX_ER, TX_EN hold from TX_CLK	0			ns
100M RMII Leader Timing
	RMII leader clock period		20		ns
	RMII leader clock duty cycle	35		65	%
100M RMII Follower Timing
T2	TX_D[1:0], TX_ER, TX_EN setup to reference clock rising. Refer to RMII Transmit Timing.	4			ns
T3	TX_D[1:0], TX_ER, TX_EN hold from reference clock rising. Refer to RMII Transmit Timing.	2			ns
T4	RX_D[1:0], RX_ER, CRS_DV delay from reference clock rising. Refer to RMII Receive Timing.	4		14	ns
SMI Timing
T1	MDC to MDIO (output) delay time	0		13	ns
T2	MDIO (input) to MDC setup time	10			ns
T3	MDIO (input) to MDC hold time	10			ns
T4	MDC frequency		2.5	24	MHz
Output Clock Timing (50M RMII Leader Clock)
	Frequency (PPM)			50	ppm
	Jitter (Long term 500 cycles)			450	ps
	Rise / Fall time			5	ns
	Duty cycle	40		60	%
Output Clock Timing (25M Clockout)
	Frequency (PPM)			50	ppm
	Duty cycle	35		65	%
	Rise time			4000	ps
	Fall time			5000	ps
	Jitter (long term: 500 cycles)			300	ps
	Jitter (short term)			250	ps
	Frequency		25		MHz
25MHz Input Clock Tolerance
	Frequency tolerance (Same as 'PLL ouptut frequency PPM' from ElectChar_Sections)	–50		50	ppm
	Rise / Fall time			5	ns
	Jitter tolerance (RMS)			50	ps
	Input phase noise at 1kHz			–98	dBc/Hz
	Input phase noise at 10kHz			–113	dBc/Hz
	Input phase noise at 100kHz			–113	dBc/Hz
	Input phase noise at 1MHz			–113	dBc/Hz
	Input phase noise at 10MHz			–113	dBc/Hz
	Duty cycle	40		60	%
50MHz Input Clock tolerance
	Frequency tolerance	–50		50	ppm
	Rise / Fall time			5	ns
	Jitter tolerance (RMS)			50	ps
	Jitter tolerance long term jitter derived from Phase Noise ( 100,000 Cycles)				ps
	Input phase noise at 1kHz			–87	dBc/Hz
	Input phase noise at 10kHz			–107	dBc/Hz
	Input phase noise at 100kHz			–107	dBc/Hz
	Input phase noise at 1MHz			–107	dBc/Hz
	Input phase noise at 10MHz			–107	dBc/Hz
	Duty cycle	40		60	%
Latency Timing
	MII 100M Tx (MII to MDI): Rising edge TX_CLK with assertion TX_EN to SSD symbol on MDI, FAST RX_DV enabled, 100 meter Cable	38		40	ns
	MII 100 Rx (MDI to MII): SSD symbol on MDI to Rising edge of RX_CLK with assertion of RX_DV, FAST RX_DV enabled, 100 meter Cable	166		170	ns
	MII 10M Tx (MII to MDI): Rising edge TX_CLK with assertion TX_EN to SSD symbol on MDI			540	ns
	RMII follower 100M Tx (RMII to MDI) :Follower RMII Rising edge XI clock with assertion TX_EN to SSD symbol on MDI, FAST RX_DV enabled, 100 meter Cable	88		96	ns
	RMII leader 100M Tx (RMII to MDI): Leader RMII rising edge clock with assertion TX_EN to SSD symbol on MDI, FAST RX_DV enabled, 100 meter Cable	88		96	ns
	RMII follower 10M Tx (RMII to MDI): Follower RMII rising edge XI clock with assertion TX_EN to SSD symbol on MDI			1360	ns
	RMII leader 10M Tx (RMII to MDI): Leader RMII rising edge clock with assertion TX_EN to SSD symbol on MDI			1360	ns
	MII 10M Rx (MDI to MII): SSD symbol on MDI to Rising edge of RX_CLK with assertion of RX_DV, FAST RX_DV enabled, 100 meter Cable			1640	ns
	RMII follower 100M Rx ( MDI to RMII): SSD symbol on MDI to follower RMII rising edge of XI clock with assertion of CRS_DV, FAST RX_DV enabled, 100 meter Cable	268		288	ns
	RMII leader 100M Rx (MDI to RMII): SSD symbol on MDI to leader RMII rising edge of leader clock with assertion of CRS_DV	252		270	ns
	RMII follower 10M (MDI to RMII): SSD symbol on MDI to follower RMII rising edge of XI clock with assertion of CRS_DV (10M)	2110		2152	ns
	RMII leader 10M (MDI to RMII): SSD symbol on MDI to leader RMII rising edge of leader clock with assertion of CRS_DV (10M)	2110		2152	ns
	MII : XI to TXCLK phase difference ( across Resets, Power Cycle)	0	2	4	ns

(1) Verified by Design, Production or Characterization test

(2) Clock shall be available at start of power ramp of supplies. If clock is delayed, additional RESET_N is needed post POR completion. Reset can be initiated after 100µs of clock stabilization and POR completion

(3) While receiving first nibble of data, PHY switches source from local to recovered clock causing RX_CLK to stretch and impacting the RX_CLK to RX_DV delay

(4) Both VDDIO or AVDD supply can ramp together or ramp of any of them can be delayed upto max value)

(5) Enable Rx_Error count or Signal/Energy Loss indication to meet maximum limit