SNLS647G december   2019  – july 2023 DP83826E , DP83826I

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Mode Comparison Tables
  7. 6 Pin Configuration and Functions (ENHANCED Mode)
  8. 7 Pin Configuration and Functions (BASIC Mode)
  9. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Timing Diagrams
    8. 8.8 Typical Characteristics
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Auto-Negotiation (Speed/Duplex Selection)
      2. 9.3.2  Auto-MDIX Resolution
      3. 9.3.3  Energy Efficient Ethernet
        1. 9.3.3.1 EEE Overview
        2. 9.3.3.2 EEE Negotiation
      4. 9.3.4  EEE for Legacy MACs Not Supporting 802.3az
      5. 9.3.5  Wake-on-LAN Packet Detection
        1. 9.3.5.1 Magic Packet Structure
        2. 9.3.5.2 Magic Packet Example
        3. 9.3.5.3 Wake-on-LAN Configuration and Status
      6. 9.3.6  Low Power Modes
        1. 9.3.6.1 Active Sleep
        2. 9.3.6.2 IEEE Power-Down
        3. 9.3.6.3 Deep Power Down State
      7. 9.3.7  RMII Repeater Mode
      8. 9.3.8  Clock Output
      9. 9.3.9  Media Independent Interface (MII)
      10. 9.3.10 Reduced Media Independent Interface (RMII)
      11. 9.3.11 Serial Management Interface
        1. 9.3.11.1 Extended Register Space Access
        2. 9.3.11.2 Write Address Operation
        3. 9.3.11.3 Read Address Operation
        4. 9.3.11.4 Write (No Post Increment) Operation
        5. 9.3.11.5 Read (No Post Increment) Operation
        6. 9.3.11.6 Example Write Operation (No Post Increment)
      12. 9.3.12 100BASE-TX
        1. 9.3.12.1 100BASE-TX Transmitter
          1. 9.3.12.1.1 Code-Group Encoding and Injection
          2. 9.3.12.1.2 Scrambler
          3. 9.3.12.1.3 NRZ to NRZI Encoder
          4. 9.3.12.1.4 Binary to MLT-3 Converter
        2. 9.3.12.2 100BASE-TX Receiver
      13. 9.3.13 10BASE-Te
        1. 9.3.13.1 Squelch
        2. 9.3.13.2 Normal Link Pulse Detection and Generation
        3. 9.3.13.3 Jabber
        4. 9.3.13.4 Active Link Polarity Detection and Correction
      14. 9.3.14 Loopback Modes
        1. 9.3.14.1 Near-end Loopback
        2. 9.3.14.2 MII Loopback
        3. 9.3.14.3 PCS Loopback
        4. 9.3.14.4 Digital Loopback
        5. 9.3.14.5 Analog Loopback
        6. 9.3.14.6 Far-End (Reverse) Loopback
      15. 9.3.15 BIST Configurations
      16. 9.3.16 Cable Diagnostics
        1. 9.3.16.1 Time Domain Reflectometry (TDR)
        2. 9.3.16.2 Fast Link-Drop Functionality
      17. 9.3.17 LED and GPIO Configuration
    4. 9.4 Programming
      1. 9.4.1 Hardware Bootstraps Configuration
        1. 9.4.1.1 DP83826 Bootstrap Configurations (ENHANCED Mode)
          1. 9.4.1.1.1 Bootstraps for PHY Address
        2. 9.4.1.2 DP83826 Strap Configuration (BASIC Mode)
          1. 9.4.1.2.1 Bootstraps for PHY Address
    5. 9.5 Register Maps
      1. 9.5.1 DP83826 Registers
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Twisted-Pair Interface (TPI) Network Circuit
      2. 10.2.2 Transformer Recommendations
      3. 10.2.3 Capacitive DC Blocking
      4. 10.2.4 Design Requirements
        1. 10.2.4.1 Clock Requirements
          1. 10.2.4.1.1 Oscillator
          2. 10.2.4.1.2 Crystal
      5. 10.2.5 Detailed Design Procedure
        1. 10.2.5.1 MII Layout Guidelines
        2. 10.2.5.2 RMII Layout Guidelines
        3. 10.2.5.3 MDI Layout Guidelines
      6. 10.2.6 Application Curves
  12. 11Power Supply Recommendations
  13. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Signal Traces
      2. 12.1.2 Return Path
      3. 12.1.3 Transformer Layout
      4. 12.1.4 Metal Pour
      5. 12.1.5 PCB Layer Stacking
        1. 12.1.5.1 Layout Example
  14. 13Device and Documentation Support
    1. 13.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Support Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  15. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.6 Timing Requirements

(1)
PARAMETER MIN NOM MAX UNIT
Power Up Timing
T1 Voltage Ramp Duration ( 0% to 100% VDDIO) 0.5 50 ms
T2, (2) Supply Sequencing VDDA3V3 followed by VDDIO or VDDIO followed by VDDA3V3 (5) 0 200 ms
T3 Voltage Ramp Duration ( 0% to 100% of VDDA3V3) 0.5 50 ms
T4 POR release time / Powerup to SMI ready: Post power-up stabilization time prior to MDC preamble for register access 50 ms
T5 Powerup to FLP 1500 ms
Pedestal Voltage on VDDA3V3, VDDIO before Power Ramp 0.3 V
Reset Timing
T1 RESET PULSE Width: Miminum Reset pulse width to be able to reset (w/o debouncing caps) 25 us
T2 Reset to SMI ready: Post reset stabilization time prior to MDC preamble for register access 2 ms
T3 Reset to FLP 1500 ms
Reset to 100M signaling (strapped mode) 0.5 ms
Reset to RMII Master clock 0.2 ms
Fast Link Pulse Timing
T1 Clock Pulse to Clock Pulse Period 111 125 139 μs
T2 Clock Pulse to Data Pulse Period 55.5 62.5 69.5 μs
T3 Clock/Data Pulse Width 104 ns
T4 FLP Burst to FLP Burst Period 8 16 24 ms
T5 FLP Burst Width 2 ms
Pulse in Burst Width 17 33
Link Up Timing
Fast Link Drop enabled using straps , 150 meter cable 10 us
Fast Link Drop Time using Mode 1 (Signal/Energy Loss indication) 10 us
Fast Link Drop Time using Mode 2 (Low SNR Threshold) 10 us
Fast Link Drop Time using Mode 3 (MLT3 Error count)(4) 10 us
Fast Link Drop Time using Mode 4 (RX Error count) 10 us
Fast Link Drop Time using Mode 5 (Descrambler link drop)(4) 11 us
100M EEE timings
Sleep time 210 us
Quiet time 20 ms
Wake Time (Tw_sys_tx)  36 us
Refresh time 200 us
100M MII Receive Timing
T1  RX_CLK High / Low Time 16 20 24 ns
T2 RX_D[3:0], RX_ER, RX_DV Delay from RX_CLK rising 10 30 ns
100M MII Transmit Timing
T1 TX_CLK High / Low Time 16 20 24 ns
T2 TX_D[3:0], TX_ER, TX_EN Setup to TX_CLK 10 ns
T3 TX_D[3:0], TX_ER, TX_EN Hold from TX_CLK 0 ns
10M MII Receive Timing
T1 RX_CLK High / Low Time(3) 160 200 240 ns
T2 RX_D[3:0], RX_ER, RX_DV Delay from RX_CLK rising(3) 100 300 ns
10M MII Transmit Timing
T1 TX_CLK High / Low Time 190 200 210 ns
T2 TX_D[3:0], TX_ER, TX_EN Setup to TX_CLK 25 ns
T3 TX_D[3:0], TX_ER, TX_EN Hold from TX_CLK 0 ns
100M RMII Master Timing 
RMII Master Clock Period 20 ns
RMII Master Clock Duty Cycle 35 65 %
100M RMII Timing
T2 TX_D[1:0], TX_ER, TX_EN Setup to Reference Clock rising 4 ns
T3 TX_D[1:0], TX_ER, TX_EN Hold from Reference Clock rising 2 ns
T4 RX_D[1:0], RX_ER, CRS_DV Delay from Reference Clock rising 4 14 ns
SMI Timing
T1 MDC to MDIO (Output) Delay Time 0 13 ns
T2 MDIO (Input) to MDC Setup Time 10 ns
T3 MDIO (Input) to MDC Hold Time 10 ns
T4 MDC Frequency 2.5 24 MHz
Output Clock Timing (50M RMII Master Clock)
Frequency (PPM) 50 ppm
Jitter (Long Term 500 Cyles) 450 ps
Rise / Fall Time 5 ns
Duty Cycle 40 60 %
Output Clock Timing (25M Clockout)
Frequency (PPM) 50 ppm
Duty Cycle 35 65 %
Rise time 4000 ps
Fall Time 5000 ps
Jitter (Long Term: 500 Cycles)  300 ps
Jitter ( Short Term) 250 ps
Frequency 25 MHz
25MHz Input Clock Tolerance
Frequency Tolerance -100 100 ppm
Rise / Fall Time 5 ns
Jitter Tolerance (RMS) 50 ps
Input phase noise at 1 kHz -98 dBc/Hz
Input phase noise at 10 kHz -113 dBc/Hz
Input phase noise at 100 kHz -113 dBc/Hz
Input phase noise at 1 MHz -113 dBc/Hz
Input phase noise at 10 MHz -113 dBc/Hz
Duty Cycle 40 60 %
50MHz Input Clock tolerance
Frequency Tolerance -100 100 ppm
Rise / Fall Time 5 ns
Jitter Tolerance (RMS) 50 ps
Jitter Tolerance Long Term Jitter derived from Phase Noise ( 100,000 Cycles) ps
Input phase noise at 1 kHz -87 dBc/Hz
Input phase noise at 10 kHz -107 dBc/Hz
Input phase noise at 100 kHz -107 dBc/Hz
Input phase noise at 1 MHz -107 dBc/Hz
Input phase noise at 10 MHz -107 dBc/Hz
Duty Cycle 40 60 %
Latency Timing
MII 100M Tx (MII to MDI): Rising edge TX_CLK with assertion TX_EN to SSD symbol on MDI, FAST RX_DV enabled, 100 meter Cable 38 40 ns
MII 100 Rx (MDI to MII): SSD symbol on MDI to Rising edge of RX_CLK with assertion of RX_DV, FAST RX_DV enabled, 100 meter Cable 166 170 ns
MII 10M Tx (MII to MDI): Rising edge TX_CLK with assertion TX_EN to SSD symbol on MDI 540 ns
RMII Slave 100M Tx (RMII to MDI) :Slave RMII Rising edge XI clock with assertion TX_EN to SSD symbol on MDI, FAST RX_DV enabled, 100 meter Cable 88 96 ns
RMII Master 100M Tx (RMII to MDI) Master RMII Rising edge clock with assertion TX_EN to SSD symbol on MDI, FAST RX_DV enabled, 100 meter Cable 88 96 ns
RMII Slave 10M Tx(RMII to MDI ) : Slave RMII Rising edge XI clock with assertion TX_EN to SSD symbol on MDI 1360 ns
RMII Master 10M Tx (RMII to MDI)Master RMII Rising edge clock with assertion TX_EN to SSD symbol on MDI  1360 ns
MII 10M Rx (MDI to MII): SSD symbol on MDI to Rising edge of RX_CLK with assertion of RX_DV, FAST RX_DV enabled, 100 meter Cable 1640 ns
RMII Slave 100M Rx ( MDI to RMII) : SSD symbol on MDI to Slave RMII Rising edge of XI clock with assertion of CRS_DV, FAST RX_DV enabled, 100 meter Cable 268 288 ns
RMII Master 100M Rx ( MDI to RMII): SSD symbol on MDI to Master RMII Rising edge of Master clock with assertion of CRS_DV 252 270 ns
RMII Slave 10M (MDI to RMII) :SSD symbol on MDI to Slave RMII Rising edge of XI clock with assertion of CRS_DV (10M) 2110
2152 ns
RMII Master 10M ( MDI to RMII) : SSD symbol on MDI to Master RMII Rising edge of Master clock with assertion of CRS_DV (10M) 2110 2152 ns
MII : XI to TXCLK phase difference ( across Resets, Power Cycle) 0 2 4 ns
(1) Ensured by Design, Production or Characterisation test
(2) Clock shall be available at start of power ramp of supplies. If Clock is delayed, additional RESET_N is needed post POR completion. Reset can be initiated after 100 usec of Clock stablisation and POR completion
(3) While receiving first nibble of data, PHY switches source from local to recovered clock. It causes stretching of RX_CLK and  RX_CLK  to RX_DV delay
(4) MLT3 and Descrambler fast link drop requires additional configuration. Refer to features section
(5) Both VDDIO or AVDD supply can ramp together or ramp of any of them can be delayed upto max value)