SNLS647G december   2019  – july 2023 DP83826E , DP83826I

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Mode Comparison Tables
  7. 6 Pin Configuration and Functions (ENHANCED Mode)
  8. 7 Pin Configuration and Functions (BASIC Mode)
  9. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Timing Diagrams
    8. 8.8 Typical Characteristics
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Auto-Negotiation (Speed/Duplex Selection)
      2. 9.3.2  Auto-MDIX Resolution
      3. 9.3.3  Energy Efficient Ethernet
        1. 9.3.3.1 EEE Overview
        2. 9.3.3.2 EEE Negotiation
      4. 9.3.4  EEE for Legacy MACs Not Supporting 802.3az
      5. 9.3.5  Wake-on-LAN Packet Detection
        1. 9.3.5.1 Magic Packet Structure
        2. 9.3.5.2 Magic Packet Example
        3. 9.3.5.3 Wake-on-LAN Configuration and Status
      6. 9.3.6  Low Power Modes
        1. 9.3.6.1 Active Sleep
        2. 9.3.6.2 IEEE Power-Down
        3. 9.3.6.3 Deep Power Down State
      7. 9.3.7  RMII Repeater Mode
      8. 9.3.8  Clock Output
      9. 9.3.9  Media Independent Interface (MII)
      10. 9.3.10 Reduced Media Independent Interface (RMII)
      11. 9.3.11 Serial Management Interface
        1. 9.3.11.1 Extended Register Space Access
        2. 9.3.11.2 Write Address Operation
        3. 9.3.11.3 Read Address Operation
        4. 9.3.11.4 Write (No Post Increment) Operation
        5. 9.3.11.5 Read (No Post Increment) Operation
        6. 9.3.11.6 Example Write Operation (No Post Increment)
      12. 9.3.12 100BASE-TX
        1. 9.3.12.1 100BASE-TX Transmitter
          1. 9.3.12.1.1 Code-Group Encoding and Injection
          2. 9.3.12.1.2 Scrambler
          3. 9.3.12.1.3 NRZ to NRZI Encoder
          4. 9.3.12.1.4 Binary to MLT-3 Converter
        2. 9.3.12.2 100BASE-TX Receiver
      13. 9.3.13 10BASE-Te
        1. 9.3.13.1 Squelch
        2. 9.3.13.2 Normal Link Pulse Detection and Generation
        3. 9.3.13.3 Jabber
        4. 9.3.13.4 Active Link Polarity Detection and Correction
      14. 9.3.14 Loopback Modes
        1. 9.3.14.1 Near-end Loopback
        2. 9.3.14.2 MII Loopback
        3. 9.3.14.3 PCS Loopback
        4. 9.3.14.4 Digital Loopback
        5. 9.3.14.5 Analog Loopback
        6. 9.3.14.6 Far-End (Reverse) Loopback
      15. 9.3.15 BIST Configurations
      16. 9.3.16 Cable Diagnostics
        1. 9.3.16.1 Time Domain Reflectometry (TDR)
        2. 9.3.16.2 Fast Link-Drop Functionality
      17. 9.3.17 LED and GPIO Configuration
    4. 9.4 Programming
      1. 9.4.1 Hardware Bootstraps Configuration
        1. 9.4.1.1 DP83826 Bootstrap Configurations (ENHANCED Mode)
          1. 9.4.1.1.1 Bootstraps for PHY Address
        2. 9.4.1.2 DP83826 Strap Configuration (BASIC Mode)
          1. 9.4.1.2.1 Bootstraps for PHY Address
    5. 9.5 Register Maps
      1. 9.5.1 DP83826 Registers
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Twisted-Pair Interface (TPI) Network Circuit
      2. 10.2.2 Transformer Recommendations
      3. 10.2.3 Capacitive DC Blocking
      4. 10.2.4 Design Requirements
        1. 10.2.4.1 Clock Requirements
          1. 10.2.4.1.1 Oscillator
          2. 10.2.4.1.2 Crystal
      5. 10.2.5 Detailed Design Procedure
        1. 10.2.5.1 MII Layout Guidelines
        2. 10.2.5.2 RMII Layout Guidelines
        3. 10.2.5.3 MDI Layout Guidelines
      6. 10.2.6 Application Curves
  12. 11Power Supply Recommendations
  13. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Signal Traces
      2. 12.1.2 Return Path
      3. 12.1.3 Transformer Layout
      4. 12.1.4 Metal Pour
      5. 12.1.5 PCB Layer Stacking
        1. 12.1.5.1 Layout Example
  14. 13Device and Documentation Support
    1. 13.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Support Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  15. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.1 Overview

The DP83826 is a single-port physical layer transceiver compliant to IEEE802.3 10BASE-Te and 100BASE-TX standards. The DP83826 is designed to meet stringent Industrial fieldbus applications' needs and offers very low latency, deterministic variation in latency (across reset, power cycle), fixed phase between XI and TX_CLK, low power, and configuration using hardware bootstraps to achieve fast link up. The device supports the standard MII and RMII (Master mode and Slave mode) for direct connection to the media access controller (MAC). Its dedicated CLKOUT pin can be used to clock other modules on the system. In addition, the PWRDN pin controls the DP83826 link up from power-on-reset (POR) and helps with design of asynchronous power-up of the DP83826 and host system-on-a-chip (SoC) or field-programmable-gate-array (FPGA) controller.

The device operates from a single 3.3-V power supply and has an integrated LDO to provide voltage rails needed for internal blocks. The device allows I/O voltage interfaces of 3.3 V or 1.8 V, which in turn enables the DP83826 to operate as a single-supply PHY. Automatic supply configuration within the DP83826 allows for any combination of VDDIO supply without the need for additional configuration settings.

The DP83826 uses mixed-signal processing to perform equalization, data recovery, and error correction to achieve robust operation over a CAT5e twisted-pair cable length greater than 150 meters.

DP83826 offers two modes selectable during the power-up sequence using hardware bootstraps.

  • BASIC mode
  • ENHANCED mode

BASIC mode provides all the features required for standard Ethernet applications, using a common pinout configuration used in many of today's applications. This makes it easy to evaluate and test the product on existing platforms. The integrated MAC and MDI terminations streamline the design of boards when using the DP83826. All the required clock outputs are generated from a single PLL with a 25-MHz external crystal or oscillator input.

Note: For a step-by-step approach on using the DP83826 BASIC mode in existing systems that use a common standard Ethernet pinout, please refer to SNLA338.

ENHANCED mode includes all the modes of operation described in BASIC Mode, however, the change in pins enable additional features. This makes it easy to use the DP83826 in ENHANCED Mode for Ethernet fieldbus applications in addition to the standard Ethernet applications. The feature includes:

  • Dedicated Reference Clock Output: CLKOUT (pin 31) can be used to synchronize the whole system resulting in lower latency (reduced FIFO on MAC). This clock is enabled at POR and remains available across the reset. It also reduces the need for a dedicated clock for other PHYs and the host SoC/FPGA on the board.
  • Dedicated HW Strap to use Force Mode, MDI or MDIX for fast link-up from POR and Reset.
  • IEEE Power Down Pin: PWRDN (pin 21) helps asynchronous power-up of the DP83826 and host SoC/FPGA control, and can still manage the DP83826 link-up through this dedicated pin.
  • PHY address hardware bootstraps on non MAC interface pins to improve Signal Integrity on MII and RMII MAC interface pins.

For pin maps of both modes, refer to section Section 6and Section 7.

To configure the hardware bootstraps for both modes, refer to sections Section 9.4.1.1 and Section 9.4.1.2.