SLVSJF0 October   2025 DRV7167

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information_DRV7167A
    5. 5.5 Electrical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Propagation Delay and Mismatch Measurement
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Control Inputs
      2. 7.3.2 Start-up and UVLO
      3. 7.3.3 Bootstrap Supply Regulation
      4. 7.3.4 Level Shift
      5. 7.3.5 Zero Voltage Detection (ZVD) Reporting
      6. 7.3.6 Short Circuit Protection (SCP)
      7. 7.3.7 Over Temperature Detection (OTD)
      8. 7.3.8 Fault Indication
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Typical Application - PWM Mode
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Examples
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Package Information
      1. 11.1.1 Mechanical Data

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.6 Short Circuit Protection (SCP)

The DRV7167A implements drain-to-source voltage, VDS, monitoring based short-circuit proteciton on both FETs. After either FET is turned on through HI/LI=high, the device waits for a time tBLANK, following which the VDSvoltage of the FET is sensed. If the voltage is greater than VDSAT, a short circuit is inferred. Thereafter the FET is turned off to prevent damage. This protection operates on a cycle-by-cycle basis. That is, every HI/LI logic low-to-high cycle turns on the FET. If the VDS exceeds the set threshold, the short circuit protection turns off the FET for the remainder of the HI/LI logic-high duration.