SLVSFU5B February   2020  – August 2021 DRV8220

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 External Components
      2. 8.3.2 Control Modes
        1. 8.3.2.1 PWM Control Mode (DSG: MODE = 0 and DRL)
        2. 8.3.2.2 PH/EN Control Mode (DSG: MODE = 1)
        3. 8.3.2.3 Half-Bridge Control Mode (DSG: MODE = Hi-Z)
      3. 8.3.3 Protection Circuits
        1. 8.3.3.1 Supply Undervoltage Lockout (UVLO)
        2. 8.3.3.2 OUTx Overcurrent Protection (OCP)
        3. 8.3.3.3 Thermal Shutdown (TSD)
      4. 8.3.4 Pin Diagrams
        1. 8.3.4.1 Logic-Level Inputs
        2. 8.3.4.2 Tri-Level Input
    4. 8.4 Device Functional Modes
      1. 8.4.1 Active Mode
      2. 8.4.2 Low-Power Sleep Mode
      3. 8.4.3 Fault Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Full-Bridge Driving
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Supply Voltage
          2. 9.2.1.2.2 Control Interface
          3. 9.2.1.2.3 Low-Power Operation
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Half-Bridge Driving
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 Supply Voltage
          2. 9.2.2.2.2 Control Interface
          3. 9.2.2.2.3 Low-Power Operation
        3. 9.2.2.3 Application Curves
      3. 9.2.3 Dual-Coil Relay Driving
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
          1. 9.2.3.2.1 Supply Voltage
          2. 9.2.3.2.2 Control Interface
          3. 9.2.3.2.3 Low-Power Operation
        3. 9.2.3.3 Application Curves
      4. 9.2.4 Current Sense
        1. 9.2.4.1 Design Requirements
        2. 9.2.4.2 Detailed Design Procedure
          1. 9.2.4.2.1 Shunt Resistor Sizing
          2. 9.2.4.2.2 RC Filter
    3. 9.3 Current Capability and Thermal Performance
      1. 9.3.1 Power Dissipation and Output Current Capability
      2. 9.3.2 Thermal Performance
        1. 9.3.2.1 Steady-State Thermal Performance
        2. 9.3.2.2 Transient Thermal Performance
  10. 10Power Supply Recommendations
    1. 10.1 Bulk Capacitance
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5 Electrical Characteristics

4.5 V ≤ VVM ≤ 18 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted).
Typical values are at TJ = 27°C and VVM = 12 V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLY (VM)
IVM VM active mode current IN1 = 0 V, IN2 = 3.3 V 1.5 2 mA
IVMQ VM sleep mode current Sleep mode, VVM = 12 V, TJ = 27°C 960 nA
tWAKE Turnon time Sleep mode to active mode delay 65 μs
tAUTOSLEEP Autosleep turnoff time Active mode to autosleep mode delay,
nSLEEP = 3.3 V		 0.9 2.6 ms
tSLEEP Turnoff time Active mode to sleep mode delay, nSLEEP = 0 V 1 μs
LOGIC-LEVEL INPUTS (INx, nSLEEP, IN1/PH, IN2/EN)
VIL Input logic low voltage 0 0.35 V
VIH Input logic high voltage 1.45 5.5 V
VHYS Input logic hysteresis 49 mV
IIL Input logic low current VI = 0 V -1 1 µA
IIH Input logic high current, IN1/EN, IN2/PH VI = 3.3 V 20 50 µA
IIH_nSLEEP Input logic high current, nSLEEP VI = 3.3 V, active mode 60 100 µA
VI = 3.3 V, autosleep mode 42 nA
RPD Input pulldown resistance, IN1/EN, IN2/PH To GND 100 kΩ
TRI-LEVEL INPUTS (MODE)
VTIL Tri-level input logic low voltage 0 0.22 × VnSLEEP V
VTIZ Tri-level input Hi-Z voltage RI = Hi-Z 0.6 × VnSLEEP 0.675 × VnSLEEP V
VTIH Tri-level input logic high voltage 0.75 × VnSLEEP 5.5 V
RTPD Tri-level pulldown resistance to GND, sleep mode 1 MΩ
to GND, active mode 130 kΩ
RTPU Tri-level pullup resistance to nSLEEP buffered reference 75 kΩ
DRIVER OUTPUTS (OUTx)
RDS(on)_HS High-side MOSFET on resistance IO = 0.2 A 500 mΩ
RDS(on)_LS Low-side MOSFET on resistance IO = –0.2 A 500 mΩ
VSD Body diode forward voltage IO = –0.5 A 1 V
tRISE Output rise time VOUTx rising from 10% to 90% of VVM 150 ns
tFALL Output fall time VOUTx falling from 90% to 10% of VVM 150 ns
tPD Input to output propagation delay Input crosses 0.8 V to VOUTx = 0.1×VVM, IO = 1 A 135 ns
tDEAD Output dead time Internal dead time 500 ns
IOUT Leakage current into OUTx OUTx is Hi-Z, RL = 20 Ω to VM 186 μA
OUTx is Hi-Z, RL = 20 Ω to GND -3 nA
PROTECTION CIRCUITS
VUVLO VM supply undervoltage lockout (UVLO) Supply rising 4.5 V
Supply falling 3.7 V
VUVLO_HYS Supply UVLO hysteresis Rising to falling threshold 325 mV
tUVLO Supply undervoltage deglitch time VVM falling to OUTx disabled 11 µs
IOCP Overcurrent protection trip point 1.76 A
tOCP Overcurrent protection deglitch time 4.2 µs
tRETRY Overcurrent protection retry time 1.7 ms
TTSD Thermal shutdown temperature 153 193 °C
THYS Thermal shutdown hysteresis 22 °C