SNLS582C June   2017  – September 2020 FPC402

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Host-Side Control Interface
      2. 8.3.2  LED Control
      3. 8.3.3  Low-Speed Output Signal Control
      4. 8.3.4  Low-Speed Input Status and Interrupt Generation
      5. 8.3.5  Downstream (Port-Side) I2C Master
      6. 8.3.6  Data Prefetch From Modules
      7. 8.3.7  Scheduled Write
      8. 8.3.8  Protocol Timeouts
      9. 8.3.9  General-Purpose Inputs and Outputs
      10. 8.3.10 Hot-Plug Support
    4. 8.4 Device Functional Modes
      1. 8.4.1 I2C Host-Side Control Interface
      2. 8.4.2 SPI Host-Side Control Interface
        1. 8.4.2.1 SPI Frame Structure
        2. 8.4.2.2 SPI Read Operation
        3. 8.4.2.3 SPI Write Operation
    5. 8.5 Programming
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 SFP/QSFP Port Management
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Sequencing
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Recommended Package Footprint
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.7 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)
MINTYPMAXUNIT
DOWNSTREAM MASTER I2C SWITCHING CHARACTERISTICS
fSCLSCL clock frequencyApplies to standard-mode I2C, 100 kHz6683100kHz
Applies to fast-mode I2C, 400 kHz264332400
tLOW-SCLSCL clock pulse width low period1.3μs
tHIGH-SCLSCL clock pulse width high period0.6μs
tBUFTime bus free before new transmission startsBetween STOP and START and between ACK and RESTART20μs
tHD-STAHold time START operation0.6μs
tSU-STASetup time START operation0.6μs
tHD-DATData hold time0μs
tSU-DATData setup time0μs
tRSCL and SDA rise time100-KHz operation. From VIL (Max) – 0.15 V to VIH (Min) + 0.15 V.300ns
100-KHz operation. From VIL (Max) – 0.15 V to VIH (Min) + 0.15 V.300
tFSCL and SDA fall time 100-KHz operation. From VIH (Min) + 0.15 V to VIL (Max) – 0.15 V.300ns
400-KHz operation. From VIH (Min) + 0.15 V to VIL (Max) – 0.15 V.300
tSU-STOSTOP condition setup time0.6μs
tSP-I2C(1)Pulse width of spikes that are suppressed by FPC402 input filter050ns
(1) These parameters are not production tested.