SNLS582C June   2017  – September 2020 FPC402

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Host-Side Control Interface
      2. 8.3.2  LED Control
      3. 8.3.3  Low-Speed Output Signal Control
      4. 8.3.4  Low-Speed Input Status and Interrupt Generation
      5. 8.3.5  Downstream (Port-Side) I2C Master
      6. 8.3.6  Data Prefetch From Modules
      7. 8.3.7  Scheduled Write
      8. 8.3.8  Protocol Timeouts
      9. 8.3.9  General-Purpose Inputs and Outputs
      10. 8.3.10 Hot-Plug Support
    4. 8.4 Device Functional Modes
      1. 8.4.1 I2C Host-Side Control Interface
      2. 8.4.2 SPI Host-Side Control Interface
        1. 8.4.2.1 SPI Frame Structure
        2. 8.4.2.2 SPI Read Operation
        3. 8.4.2.3 SPI Write Operation
    5. 8.5 Programming
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 SFP/QSFP Port Management
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Sequencing
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Recommended Package Footprint
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.2.1.1 Design Requirements

For this design example, the following guidelines outlined in Table 9-1 apply.

Table 9-1 SFP/QSFP Application Design Guidelines
DESIGN PARAMETERREQUIREMENT
FPC402 physical placement

The FPC402 package is small enough to fit underneath an SFP or QSFP cage, on the opposite side of the board.

For SFP applications, such a placement leaves 4.6 mm of air gap between the FPC402 package edge and the SFP pressfit pins (assuming 14.25 mm pin-to-pin spacing for a stacked SFP cage).

For QSFP applications, such a placement leaves 7.2 mm of air gap between the FPC402 package edge and the QSFP pressfit pins (assuming 19.5 mm pin-to-pin spacing for a stacked QSFP cage).

LED implementationThe FPC402 is designed to drive active-low LEDs which have their anode connected to the port-side 3.3 V supply. Refer to Section 8.3.2.
Port-side I2C SDA and SCL pullupsAs per the SFF-8431 and SFF-8436 specification, the port-side (downstream) SCL and SDA nets must be pulled up to 3.3 V using resistors in the 4.7-kΩ to 10-kΩ range.
SFP Rate Select, RS0 and RS1

The SFP module provides two inputs RS0 and RS1 that can optionally be used for rate selection. RS0 controls the receive path signaling rate capability, and RS1 controls the transmit path signaling rate capability. In the vast majority of applications, the receive and transmit rates will coincide, and RS0 and RS1 can be controlled by the same pin on the FPC402: OUT_B.

For applications where RS0 and RS1 must be controlled independently, the GPIO[3:0] pins can be used in conjunction with OUT_B[3:0] to control both RS0 and RS1.

QSFP ModSelLQSFP provides a mechanism to enable or disable the port’s I2C interface. Because the FPC402 has a separate I2C master to communicate with each port, the ModSelL input for every QSFP can be connected to GND, thereby permanently enabling each QSFP port’s I2C bus.
SFP/QSFP port power supply de-couplingFollow the SFF-8431 and SFF-8436 recommendations for power supply de-coupling.