SNLS582C June   2017  – September 2020 FPC402

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Host-Side Control Interface
      2. 8.3.2  LED Control
      3. 8.3.3  Low-Speed Output Signal Control
      4. 8.3.4  Low-Speed Input Status and Interrupt Generation
      5. 8.3.5  Downstream (Port-Side) I2C Master
      6. 8.3.6  Data Prefetch From Modules
      7. 8.3.7  Scheduled Write
      8. 8.3.8  Protocol Timeouts
      9. 8.3.9  General-Purpose Inputs and Outputs
      10. 8.3.10 Hot-Plug Support
    4. 8.4 Device Functional Modes
      1. 8.4.1 I2C Host-Side Control Interface
      2. 8.4.2 SPI Host-Side Control Interface
        1. 8.4.2.1 SPI Frame Structure
        2. 8.4.2.2 SPI Read Operation
        3. 8.4.2.3 SPI Write Operation
    5. 8.5 Programming
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 SFP/QSFP Port Management
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Sequencing
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Recommended Package Footprint
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.2 LED Control

The FPC402 uses two sets of outputs, OUT_C[3:0] and OUT_D[3:0], to drive LEDs associated with the ports under its control. Most SFP and QSFP applications use one yellow and one green LED per port to indicate different link status such as link up, link down, and other link states.

LEDs must be connected to the FPC402 in an active-low fashion as shown in Figure 8-1 below. When the OUT_C or OUT_D pin drives a low voltage (VOL), the LED is illuminated. When the OUT_C or OUT_D pin drives a high voltage (VOH), the LED is off. Bi-color LEDs can be connected in a similar fashion, and each LED must have its own current-limiting resistor. The current-limiting resistor value is selected by choosing the desired maximum current through the LED and the corresponding voltage drop from the LED's current vs. voltage plot. The sum of forward voltage drop of the LED, the voltage drop across the series resistor, and the maximum VOL (0.5-V maximum for currents between 2 and 18 mA) is equal to the LED supply voltage. Note that OUT_C and OUT_D are tri-stated while the device is held in reset (during POR or while the EN pin is low), and are enabled during normal operation and drive a high voltage by default.

GUID-A2DD9703-847E-4700-8ED8-49BD8723A959-low.gifFigure 8-1 Example Connection Between OUT_C/OUT_D and Active-Low LEDs

Each port controlled by the FPC402 has a set of registers that allow the user to configure each LED into one of the following states:

  • ON
  • OFF
  • PWM (ON with programmable intensity)
  • BLINK (with programmable blink duty cycle, frequency, and ON intensity)
LED blinking is configured by setting an on and an off time. Each of these times is configured separately and have a minimum value of 2.5 ms and a maximum value of 637.5 ms for a maximum blinking period of 1.275 seconds. The pulse width modulation (PWM) duty cycle has 256 settings where 0 is completely off, and 255 is maximum brightness. Note that the PWM is 0 by default and must be configured for the LEDs to be visible in BLINK or PWM modes.

LED blinking can be synchronized across all four ports controlled by the FPC402, and the blinking can be synchronized across all ports in the system. For SPI, cross-device synchronization uses the SPI_LED_SYNC pin. One device is configured to forward its internal LED clock to this pin, and all other devices are configured to receive an external LED clock on this pin. For I2C, the first device in the CTRL4 to CTRL3 pin daisy chain is configured to output the internal LED clock to the CTLR4 pin. All other devices are configured to receive an external LED clock from the CTRL3 pin and to output the clock to the CTRL4 pin.

In some applications, it may be desirable to control more than two LEDs per port. In cases where the additional LEDs are relatively static in nature and blinking is not required, the GPIO and OUT_B pins of the FPC402 can be allocated for driving these LEDs in an active-low configuration. OUT_C and OUT_D must be connected to LEDs requiring blinking, dimming, or both, and up to two additional LEDs can be controlled per port from the GPIO and OUT_B pins. OUT_B is optionally used to drive RS0/RS1 in SFP ports or LPMode in QSFP ports. These module pins are often not used in a system and are instead pulled to 3.3 V (SFP) or GND (QSFP). The module functionality affected by these pins is anyway controllable through software. Figure 8-2 shows an example of how up to four LEDs can be controlled per port.

GUID-D189C9AD-9A18-497B-9CC8-6E3587DF8186-low.gifFigure 8-2 Example Configuration for Driving Four LEDs Per Port