SNLS582C June   2017  – September 2020 FPC402

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Host-Side Control Interface
      2. 8.3.2  LED Control
      3. 8.3.3  Low-Speed Output Signal Control
      4. 8.3.4  Low-Speed Input Status and Interrupt Generation
      5. 8.3.5  Downstream (Port-Side) I2C Master
      6. 8.3.6  Data Prefetch From Modules
      7. 8.3.7  Scheduled Write
      8. 8.3.8  Protocol Timeouts
      9. 8.3.9  General-Purpose Inputs and Outputs
      10. 8.3.10 Hot-Plug Support
    4. 8.4 Device Functional Modes
      1. 8.4.1 I2C Host-Side Control Interface
      2. 8.4.2 SPI Host-Side Control Interface
        1. 8.4.2.1 SPI Frame Structure
        2. 8.4.2.2 SPI Read Operation
        3. 8.4.2.3 SPI Write Operation
    5. 8.5 Programming
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 SFP/QSFP Port Management
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Sequencing
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Recommended Package Footprint
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5 Electrical Characteristics

TJ = –40°C to 125°C, VDD1 = 3.3 V ± 5%, VDD2 = 3.3 V ± 5% (unless otherwise noted).
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
POWER SUPPLY
WTOTALTotal device power dissipationVDD1 = VDD2 = 3.3 V, Outputs sourcing maximum current, OUT_C and OUT_D are OFF (Vout = High)90110mW
VDD1 = 3.3 V, VDD2 = 2.5 V, Outputs sourcing maximum current, OUT_C and OUT_D are OFF (Vout = High)100110
VDD1 = 3.3 V, VDD2 = 1.8 V, Outputs sourcing maximum current, OUT_C and OUT_D are OFF (Vout = High)100120
IVDD1Current consumption for VDD1 supplyVDD1 = VDD2 = 3.3 V, OUT_C and OUT_D are OFF (Vout = High)2631mA
VDD1 = VDD2 = 2.5 V, OUT_C and OUT_D are OFF (Vout = High)2732
VDD1 = 3.3 V, VDD2 = 1.8 V, OUT_C and OUT_D are OFF (Vout = High)2934
IVDD2Current consumption for VDD2 supplyVDD1 = VDD2 = 3.3 V, Outputs sourcing maximum current, OUT_C and OUT_D are OFF (Vout = High)0.20.35mA
VDD1 = 3.3 V, VDD2 = 2.5 V, Outputs sourcing maximum current, OUT_C and OUT_D are OFF (Vout = High)0.10.3
VDD1 = 3.3 V, VDD2 = 1.8 V, Outputs sourcing maximum current, OUT_C and OUT_D are OFF (Vout = High)0.10.25
Itotal-idleTotal device supply current consumption in idle mode6.5mA
LVCMOS I/O DC SPECIFICATIONS
VIHHigh level input voltageApplies to IN_A, IN_B, IN_C, PROTOCOL_SEL, and GPIO[3:0]23.465V
Applies to EN0.7 ×
VDD2		VDD2
VILLow level input voltageApplies to IN_A, IN_B, IN_C, PROTOCOL_SEL, GPIO[3:0], and EN–0.30.8V
VOHHigh level output voltageApplies to OUT_A, OUT_B, and GPIO[3:0], IOH = –2 mA2.83.465V
Applies to OUT_C and OUT_D, IOH = –50 µA2.5
VOLLow level output voltageApplies to OUT_A, OUT_B, and GPIO[3:0], IOL = 2 mAGND0.4V
Applies to OUT_C and OUT_D, IOL = 18 mAGND0.4
IIHHigh level input currentApplies to IN_A, IN_B, IN_C, and GPIO[3:0]–11µA
IILLow level input currentApplies to IN_A, IN_B, IN_C–220–170µA
Applies to GPIO[3:0]–11
tSP-LSPulse width of spikes that are suppressed by FPC402 input de-glitch filter on all IN_* low-speed pinsPulses shorter than min are suppressed, and pulses longer than the max are not suppressed.3050µs
DOWNSTREAM MASTER I2C ELECTRICAL CHARACTERISTICS (MOD_SCL AND MOD_SDA)
VOLLow level output voltageIOL = 3 mAGND0.4V
VILLow level input voltage–0.31.04V
VIHHigh level input voltage2.193.465V
Cb(1)I2C bus capacitive load1.6 kΩ pull-up resistor max200pF
HOST-SIDE I2C ELECTRICAL CHARACTERISTICS (PROTOCOL_SEL = FLOAT/HIGH)
VIHInput high level voltageSDA (CTRL2) and SCL (CTRL1)0.7 ×
VDD2		VDD2V
VILInput low level voltageSDA (CTRL2) and SCL (CTRL1)0.3 ×
VDD2		V
CIN(1)Input pin capacitanceSDA (CTRL2) and SCL (CTRL1)0.51pF
VOLLow level output voltageSDA (CTRL2) or SCL (CTRL1), IOL = 3 mAGND0.4V
ILIL Leakage currentSDA (CTRL2) or SCL (CTRL1), VIN = VDD2–11μA
Cb(1)I2C bus capacitive load550pF
HOST-SIDE SPI ELECTRICAL CHARACTERISTICS (PROTOCOL_SEL = GND)
VIHInput high level voltageSCK (CTRL1), SS_N (CTRL2), and MOSI (CTRL3)0.7 ×
VDD2		V
VILInput low level voltageSCK (CTRL1), SS_N (CTRL2), and MOSI (CTRL3)0.3 ×
VDD2		V
CIN(1)Input pin capacitanceSCK (CTRL1), SS_N (CTRL2), and MOSI (CTRL3)0.51pF
VOHHigh level output voltageMISO (CTRL4) pin, IOH = –4 mA0.7 ×
VDD2		V
VOLLow level output voltageMISO (CTRL4) pin, IOL = 4 mAGND0.4V
ILLeakage currentMOSI (CTRL3)–220–170µA
SCK (CTRL1), SS_N (CTRL2), and MISO (CTRL4)–11
CMISO(1)MISO output capacitive loadMISO (CTRL4) pin50pF
(1) These parameters are not production tested.