The FPC402 has four master I2C interfaces for managing up to four ports, referred to as downstream ports. Each downstream I2C interface can be configured to operate with an SCL clock frequency between 100 kHz and 400 kHz (maximum). The downstream I2C master supports clock stretching.

The SFF-8472 and SFF-8431 specifications define up to two logical device addresses per SFP port: 0xA0 and 0xA2. The SFF-8436 specification defines one logical device address per QSFP port: 0xA0. Both 0xA0 and 0xA2 are directly addressable by the upstream host controller by default. The directly accessible addresses may be modified through I2C writes to the FPC402 such that any valid I2C address is directly accessible. Refer to Table 8-6 (I2C) and Table 8-7 (SPI). The FPC402 uses this address mapping scheme to decode the port and device address and perform a downstream I2C read or write operation. This is known as a remote access. Remote accesses have the highest priority when accessing the downstream module. If there is an on-going periodic prefetch or scheduled write, these operations will be stopped at the next byte boundary and the remote access will be executed. The periodic prefetch or schedule write operation will be resumed after the remote access finishes. Note that the periodic prefetch will begin from the starting register offset of the prefetch range rather than where it left off during the interruption. If a remote access is attempted during an interrupt-driven prefetch, the interrupt-driven prefetch will finish and the remote access is executed afterwards. If an autonomous access (prefetch or scheduled write) occurs during a remote access, the autonomous access is executed after the remote access is completed.