SBOS946 September   2020 INA848

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Topology
      2. 8.3.2 Input Common-Mode Range
      3. 8.3.3 Input Protection
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Filter Pin
        1. 9.1.1.1 RC Filter Network
        2. 9.1.1.2 RLC Filter Network
      2. 9.1.2 Input Bias Current Return Path
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Reference Pin
        2. 9.2.2.2 Noise Analysis
          1. 9.2.2.2.1 Reference Voltage Noise Contribution
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.2.2.1 Reference Pin

The output voltage of the INA848 is developed with respect to the voltage on the reference pin (REF.)

The voltage source applied to the reference pin of the INA848 must have a low output impedance (RREF > 5 Ω). Any additional resistance at the reference pin creates an imbalance in the four resistors of the internal difference amplifier, resulting in degraded common-mode rejection ratio (CMRR).

Voltage reference devices are an excellent option for providing a low-impedance voltage source for the reference pin. However, if a resistor voltage divider generates a reference voltage, the divider must be buffered by an op amp, as shown in Figure 9-5, to avoid CMRR degradation.

GUID-20200818-CA0I-1L7R-G30V-QMKWDCMHJMLM-low.gif Figure 9-5 Buffer to drive the Reference Voltage

Often in dual-supply operation, the reference pin connects to the low-impedance system ground. The degradation effect of common-mode rejection ratio is thus neglegible as long as the output voltage (VOUT) is referred to the reference pin (REF).

In single-supply operation, the output signal is offset to a precise midsupply level (for example, 2.5 V in a 5-V supply environment). In applications where the output voltage is offset to a reference voltage but referred to system ground, the degradation effect of common-mode rejection ratio must be considered.