SBOS946 September   2020 INA848

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Topology
      2. 8.3.2 Input Common-Mode Range
      3. 8.3.3 Input Protection
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Filter Pin
        1. 9.1.1.1 RC Filter Network
        2. 9.1.1.2 RLC Filter Network
      2. 9.1.2 Input Bias Current Return Path
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Reference Pin
        2. 9.2.2.2 Noise Analysis
          1. 9.2.2.2.1 Reference Voltage Noise Contribution
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information
9.2.2.2.1 Reference Voltage Noise Contribution

Figure 9-7 shows the noise model of the reference buffer circuit given by Figure 9-5 using the OPA197 amplifier.

To compute the total noise for the reference buffer circuit, consider the thermal noise of the divider (that is a parallel network from noise perspective), the amplifier voltage noise (that is, enOPA = 5.5 nV/√Hz), and the voltage noise developed from the current noise of the amplifier (that is, inOPA = 1.5 fA/√Hz) through the divider.

GUID-20200828-CA0I-RN7G-JLXF-05Q1RLX0SRGN-low.svg Figure 9-7 Reference Voltage Noise Model

Thus the total reference noise can be derived from following equation:

Equation 6. GUID-20200828-CA0I-CGTF-R08Z-QHC2SQ40MQ2G-low.gif

The reference noise is divided by the first gain stage of 200 at the INA848 to compute the input-referred noise. For reference noise less than 80 nV/√Hz, this contribution can be neglected in the analysis. The given example results in a total reference noise of 29 nV/√Hz, and thus is neglected.